Signal descriptions – Rainbow Electronics DS1687 User Manual

Page 4

DS1685/DS1687

4 of 38

SIGNAL DESCRIPTIONS

GND, V

– DC power is provided to the device on these pins. V

is the +3V or +5V input.

SQW (Square-Wave Output) - The SQW pin provides a 32kHz square-wave output, t

REC

, after a power-

up condition has been detected. This condition sets the following bits, enabling the 32kHz output;
DV1 = 1, and E32K = 1. A square wave is output on this pin if either SQWE = 1 or E32K = 1. If E32K =
1, then 32kHz is output regardless of the other control bits. If E32K = 0, then the output frequency is
dependent on the control bits in register A. The SQW pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE
bit in register B or the E32K bit in extended register 4Bh. A 32kHz SQW signal is output when the
enable-32kHz (E32K) bit in extended register 4Bh is a logic 1 and V

is above V

. A 32kHz square

wave is also available when V

is less than V

if E32K = 1, ABE = 1, and voltage is applied to the

BAUX

pin.

AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS1685 since the bus
change from address to data occurs during the internal RAM access time. Addresses must be valid prior
to the latter portion of ALE, at which time the DS1685/DS1687 latches the address. Valid write data must
be present and held stable during the latter portion of the

pulse. In a read cycle, the DS1685/DS1687

outputs 8 bits of data during the latter portion of the

pulse. The read cycle is terminated and the bus

returns to a high-impedance state as

transitions high. The address/data bus also serves as a

bidirectional data path for the external extended RAM.

ALE (RTC Address-Strobe Input; Active High) – A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS1685/DS1687.

(RTC Read Input; Active Low) -

identifies the time period when the DS1685/DS1687 drives

the bus with RTC read data. The

signal is an enable signal for the output buffers of the clock.

(RTC Write Input; Active Low) -The

signal is an active-low signal. The

signal defines

the time period during which data is written to the addressed register.

(RTC Chip-Select Input; Active Low) – The chip-select signal must be asserted low during a bus

cycle for the RTC portion of the DS1685/DS1687 to be accessed.

must be kept in the active state

during

and

timing. Bus cycles that take place with ALE asserted but without asserting

latch

addresses. However, no data transfer occurs.

IRQ

(Interrupt-Request Output; Open Drain, Active Low) – The

IRQ

pin is an active-low output of

the DS1685/DS1687 that can be connected to the interrupt input of a processor. The

IRQ

output remains

low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is