Rainbow Electronics DS1687 - Manual (Page 22)

DS1685/DS1687
22 of 38
The RAM clear function is enabled or disabled by the RAM clear-enable bit (RCE; bank 1, register
04BH). When this bit is set to a logic 1, the 242 bytes of user RAM is cleared (all bits set to 1) when an
active-low transition is sensed on the
RCLR pin. This action has no affect on either the clock/calendar
settings or upon the contents of the extended RAM. The RAM clear flag (RF, bank 1, register 04AH) is
set when the RAM clear operation has been completed. If V
CC
is present at the time of the RAM clear and
RIE = 1, the IRQ line is also driven low upon completion. The interrupt condition can be cleared by
writing a 0 to the RF bit. The IRQ line then returns to its inactive high level, provided there are no other
pending interrupts. Once the RCLR pin is activated, all read/write accesses are locked out for a minimum
recover time, specified as t
REC
in the Electrical Characteristics section.
When RCE is cleared to 0, the RAM clear function is disabled. The state of the RCLR pin has no affect
on the contents of the user RAM, and transitions on the RCLR pin have no affect on RF.
128 x 8 EXTENDED RAM
The DS1685/DS1687 provides 128 x 8 of on-chip SRAM, which is controlled as nonvolatile storage
sustained from a lithium battery. On power-up, the RAM is taken out of write-protect status by the
internal power-OK signal (POK) generated from the write-protect circuitry.
The on-chip 128 x 8 NV SRAM is accessed by the eight multiplexed address/data lines AD7–AD0.
Access to the SRAM is controlled by two on-chip latch registers. One register is used to hold the SRAM
address and the other register is used to hold read/write data. The SRAM address space is from 00h to
7Fh.
Access to the extended 128 x 8 RAM is controlled by two of the registers shown in Figure 4. The
registers in bank 1 must first be selected by setting the DV0 bit in register A to a logic 1. The 7-bit
address of the RAM location to be accessed must be loaded into the extended RAM address register
located at 50h. Data in the addressed location may be read by performing a read operation from location
53h, or written to by performing a write operation to location 53h. Data in any addressed location may be
read or written repeatedly without changing the address in location 50h.