Rainbow Electronics ADC12048 - Manual (Page 23)

Features and Operating Modes
(Continued)
less than 1 kX and any active or reactive source circuitry
settles to 12 bits in less than 500 ns When source resist-
ance or source settling time increase beyond these limits
the acquisition time must also be increased to preserve pre-
cision
In asynchronous (SYNC-OUT) mode the acquisition time is
controlled by an internal counter The minimum acquisition
period is 9 clock cycles which corresponds to the nominal
value of 750 ns when the clock frequency is 12 MHz Bits b
4
and b 5 of the Configuration Register are used to select the
acquisition time from among four possible values (9 15 47
or 79 clock cycles) Since acquisition time in the asynchro-
nous mode is based on counting clock cycles it is also in-
versely proportional to clock frequency
T ACQ (ms) e
number of clock cycles
f CLK (MHz)
Note that the actual acquisition time will be longer than
T
ACQ
because acquisition begins either when the multiplex-
er channel is changed or when RDY goes low if the multi-
plexer channel is not changed After a read is performed
RDY goes high which starts the T
ACQ counter (see Figure
7 )
In synchronous (SYNC-IN) mode bits b
4
and b
5
are ig-
nored and the acquisition time depends on the sync signal
applied at the SYNC pin If a new MUX channel is selected
at the start of the conversion the acquisition period begins
on the active edge of the WR signal that latches in the new
MUX channel (see
Figure 7 ) If no new MUX channel is
selected the acquisition period begins on the falling edge of
RDY which occurs at the end of the previous conversion (or
at the end of an autozero or autocalibration procedure) The
acquisition period ends when SYNC goes high
To estimate the acquisition time necessary for accurate
conversions when the source resistance is greater than
1 kX use the following expression
T ACQMIN (ms) e
0 75(R S a R M a R S H )
1 kX a R
M a R
S H
e
0 75(R S a 2800)
3800
where R S is the source resistance R M is the MUX ‘‘On’’
resistance and R S H is the sample hold ‘‘On’’ resistance
If the settling time of the source is greater than 500 ns the
acquisition time should be about 300 ns longer than the
settling time for a ‘‘well-behaved’’ smooth settling charac-
teristic
FULL CALIBRATION CYCLE
A full calibration cycle compensates for the ADC’s linearity
and offset errors The converter’s DC specifications are
guaranteed only after a full calibration has been performed
A full calibration cycle is initated by writing a Ful-Cal com-
mand to the ADC12048 During a full calibration the offset
error is measured eight times averaged and a correction
coefficient is created The offset correction coefficient is
stored in an internal offset correction register
The overall Iinearity correction is achieved by correctng the
internal DAC’s capacitor mismatches Each capacitor is
compared eight times against all remaining smaller value
capacitors The errors are averaged and correction coeffi-
cients are created
Once the converter has been calibrated an arithmetic logic
unit (ALU) uses the offset and linearity correction coeffi-
cients to reduce the conversion offset and linearity errors to
within guaranteed limits
AUTO-ZERO CYCLE
During an auto-zero cycle the offset is measured only once
and a correction coefficient is created and stored in an inter-
nal offset register An auto-zero cycle is initiated by writing
an Auto-Zero command to the ADC12048
DIGITAL INTERFACE
The digital control signals are CS RD WR RDY and
STDBY Specific timing relationships are associated with
the interaction of these signals Refer to the Digital Timing
Diagrams section for detailed timing specifications The ac-
tive low RDY signal indicates when a certain event begins
and ends It is recommended that the ADC12048 should
only be accessed when the RDY signal is low It is in this
state that the ADC12048 is ready to accept a new com-
mand This will minimize the effect of noise generated by a
switching data bus on the ADC The only exception to this is
when the ADC12048 is in the standby mode at which time
the RDY is high and the STDBY signal is low
The
ADC12048 is in the standby mode at power up or when a
STANDBY command is issued A Ful-Cal Auto-Zero Reset
or Start command will get the ADC12048 out of the standby
mode This may be observed by monitoring the status of the
RDY and STDBY signals The RDY signal will go low and
the STDBY signal high when the ADC12048 leaves the
standby mode
The following describes the state of the digital control sig-
nals for each programmed event in both 8-bit and 13-bit
mode RDY should be low before each command is issued
except for the case when the device is in standby mode
FUL-CAL OR AUTO-ZERO COMMAND
8-bit mode The first write to the ADC12048 will place the
data in the lower byte of the Configuration register This byte
must set the HB bit (b
7 ) to allow access to the upper byte of
the Configuration register during the next write cycle During
the second write cycle the Ful-Cal or Auto-Zero command
must be issued The edge of the second write pulse on the
WR pin will force the RDY signal high At this time the con-
verter begins executing a full calibration or auto-zero cycle
The RDY signal will automatically go low when the full cali-
bration or auto-zero cycle is done
13-bit mode In a single write cycle the Ful-Cal or Auto-Zero
command must be written to the ADC12048 The edge of
the WR signal will force the RDY high At this time the con-
verter begins executing a full calibration or auto-zero cycle
The RDY signal will automatically go low when the full cali-
bration or auto-zero cycle is done
STARTING A CONVERSION START COMMAND
In order to completely describe the events associated with
the Start command both the SYNC-OUT and SYNC-IN
modes must be considered
SYNC-OUT Asynchronous
8-bit mode The first byte written to the ADC12048 should
set the MUX channel the acquisition time and the HB bit
The second byte should clear the SYNC bit write the
START command and clear the BW bit In order to initiate a
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