Rainbow Electronics ADC12048 - Manual (Page 22)

Functional Description
The ADC12048 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus The digital inter-
face consists of a 13-bit data input output bus (D
12 – D 0 )
digital control signals and two internal registers a write only
13-bit Configuration register and a read only 13-bit Data
register
The Configuration register programs the functionality of the
ADC12048 The 13 bits of the Configuration register are di-
vided into 7 fields Each field controls a specific function of
the ADC12048 the channel selection of the MUX the ac-
quisition time synchronous or asynchronous conversions
mode of operation and the data bus size
Features and Operating Modes
SELECTABLE BUS WIDTH
The ADC12048 can be programmed to interface with an
8-bit or 16-bit data bus The BW bit (b
12
) in the Configura-
tion register controls the bus size The bus width is set to
8 bits
(D 7 – D 0 are active and D 12 – D 8 are in TRI-STATE) if
the BW bit is cleared or 13 bits (D 12 – D 0 are active) if the
BW bit is set At power-up the bus width defaults to 8 bits
and any initial programming of the ADC12048 should take
this into consideration
In 8-bit mode the Configuration register is byte accessible
The HB bit in the lower byte of the Configuration register is
used to access the upper byte If the HB bit is set with a
write to the lower byte the next byte written to the ADC will
be placed in the upper byte of the Configuration register
After data is written to the upper byte of the Configuration
register the HB bit will automatically be cleared causing the
next byte written to the ADC to go to the lower byte of the
Configuration register When reading the ADC in 8-bit mode
the first read cycle places the lower byte of the Data register
on the data bus followed by the upper byte during the next
read cycle
In 13-bit mode the HB bit is a don’t care condition and all
bits of the data register and Configuration register are ac-
cessible with a single read or write cycle Since the bus
width of the ADC12048 defaults to 8 bits after power-up the
first action when 13-bit mode is desired must be set to the
bus width to 13 bits
WMODE
The WMODE pin is used to determine the active edge of the
write pulse The state of this pin determines which edge of
the WR signal will cause the ADC to latch in data This is
processor dependent If the processor has valid data on the
bus during the falling edge of the WR signal the WMODE
pin must be tied to V
D a This will cause the ADC to latch
the data on the falling edge of the WR signal If data is valid
on the rising edge of the WR signal the WMODE pin must
be tied to DGND causing the ADC to latch in the data on the
rising edge of the WR signal
INPUT MULTIPLEXER
The ADC12048 has an eight channel input multiplexer with
a COM input that can be used in a single-ended pseudo-dif-
ferential or fully-differential mode The MUX select bits (b
3
–
b 0 ) in the Configuration register determine which channels
will appear at the MUXOUTa and MUXOUTb multiplexer
output pins (Refer to Register Bit Description Section ) Ana-
log signal conditioning with fixed-gain amplifiers program-
mable-gain amplifiers filters and other processing circuits
can be used at the output of the multiplexer before being
applied to the ADC inputs The ADCINa and ADCINb are
the fully differential non-inverting (positive) and inverting
(negative) inputs to the analog-to-digital converter (ADC) of
the ADC12048 If no external signal conditioning is required
on the signal output of the multiplexer MUXOUTa should
be connected to ADCINa and MUXOUTb should be con-
nected to ADCINb
The analog input multiplexer can be set up to operate in
either one of eight differential or eight single-ended (the
COM input as the zero reference) modes In the differential
mode the analog inputs are paired as follows CH0 with
CH1 CH2 with CH3 CH4 with CH5 and CH6 with CH7 The
input channel pairs can be connected to the MUXOUTa
and MUXOUTb pins in any order In the single-ended
mode one of the input channels CH0 through CH7 can be
assigned to MUXOUTa while the MUXOUTb is always as-
signed to the COM input
STANDBY MODE
The ADC12048 has a low power consumption mode (75 mW
5V) This mode is entered when a Standby command is
written in the command field of the Configuration register A
logic low appearing on the STDBY output pin indicates that
the ADC12048 is in the Standby mode Any command other
than the Standby command written to the Configuration reg-
ister will get the ADC12048 out of the Standby mode The
STDBY pin will immediately switch to a logic ‘‘1’’ as soon as
the ADC12048 is requested to get out of the standby mode
The RDY pin will then be asserted low when the ADC is
actually out of the Standby mode and ready for normal oper-
ation The ADC12048 defaults to the Standby mode follow-
ing a hardware power-up This can be verified by examining
the logic low status of the STDBY pin
SYNC ASYNC MODE
The ADC12048 may be programmed to operate in synchro-
nous (SYNC-IN) or asynchronous (SYNC-OUT) mode To
enter synchronous mode the SYNC bit in the Configuration
register must be set The ADC12048 is in synchronous
mode after a hardware power-up In this mode the SYNC
pin is programmed as an input and conversions are syn-
chronized to the rising edges of the signal applied at the
SYNC pin Acquisition time can also be controlled by the
SYNC signal when in synchronous mode Refer to the sync-
in timing diagrams When the SYNC bit is cleared the ADC
is in asynchronous mode and the SYNC pin is programmed
as an output In asynchronous mode the signal at the
SYNC pin indicates the status of the converter This pin is
high when the converter is performing a conversion Refer
to the sync-out timing diagrams
SELECTABLE ACQUISITION TIME
The ADC12048’s internal sample hold circuitry samples an
input voltage by connecting the input to an internal sampling
capacitor (approximately 70 pF) through an effective resist-
ance equal to the multiplexer ‘‘On’’ resistance (300X max)
plus the ‘‘On’’ resistance of the analog switch at the input to
the sample hold circuit (2500X typical) and the effective
output resistance of the source For conversion results to be
accurate the period during which the sampling capacitor is
connected to the source (the ‘‘acquisition time’’) must be
long enough to charge the capacitor to within a small frac-
tion of an LSB of the input voltage An acquisition time of
750 ns is sufficient when the external source resistance is
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