Rainbow Electronics MAX9867 - Manual (Page 24)

MAX9867
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. See Table 3.
SDODLY is used to control the SDOUT timing. See the
Digital Audio Interface section for a detailed description.
Clock Control
The MAX9867 can work with a master clock (MCLK)
supplied from any system clock within the 10MHz-to-
60MHz range. Internally, the MAX9867 requires a
10MHz-to-20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9867. See Table 4.
The MAX9867 is capable of supporting any sample rate
from 8kHz to 48kHz, including all common sample rates
(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz). To
accommodate a wide range of system architectures,
the MAX9867 supports three main clocking modes:
• Normal: This mode uses a 15-bit clock divider coeffi-
cient to set the sample rate relative to the prescaled
MCLK input (PCLK). This allows high flexibility in both
the MCLK and LRCLK frequencies and can be used
in either master or slave mode.
• Exact Integer: In both master and slave mode, com-
mon MCLK frequencies (12MHz, 13MHz, 16MHz,
and 19.2MHz) can be programmed to operate in
exact integer mode for both 8kHz and 16kHz sample
rates. In these modes, the MCLK and LRCLK rates
are selected by using the FREQ bits instead of the NI
and PLL control bits.
• PLL: When operating in slave mode, a PLL can be
enabled to lock onto externally generated LRCLK
signals that are not integer related to PCLK. Prior to
enabling the interface, program NI to the nearest
desired ratio and set the NI[0] = 1 to enable the
PLL’s rapid lock mode. If NI[0] = 0, then NI is ignored
and PLL lock time is slower.
Ultra-Low Power Stereo Audio Codec
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REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
Interrupt Enable ICLD ISLD IULK 0 0 SDODLY IJDET 0 0x04
Table 3. Interrupt Registers
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 REGISTER
System Clock 0 0 PSCLK FREQ 0x05
Stereo Audio Clock
Control High
PLL NI[14:8] 0x06
Stereo Audio Clock
Control Low
NI[7:1] NI[0] 0x07
Table 4. Clock Control Registers
BITS FUNCTION
PSCLK
MCLK Prescaler
Divides MCLK to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz.
10 = Select if MCLK is between 20MHz and 40MHz.
11 = Select if MCLK is between 40MHz and 60MHz.