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Table 5. interrupt register, Table 6. interrupt mask register – Rainbow Electronics MAX5945 User Manual

Page 23

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MAX5945

Quad Network Power Controller

for Power-Over-LAN

______________________________________________________________________________________

23

ADDRESS = 00h

SYMBOL

BIT

R/W

DESCRIPTION

SUP_FLT

7

R

Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh
(Table 8).

TSTR_FLT

6

R

Interrupt signal for startup failures. TSRT_FLT is the logic OR of bits [7:0] in register R08h/R09h
(Table 7).

IMAX_FLT

5

R

Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register
R06h/R07h (Table 6).

CL_END

4

R

Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register
R04h/R05h (Table 5)

DET_END

3

R

Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register
R04h/R05h (Table 5).

LD_DISC

2

R

Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h
(Table 6).

PG_INT

1

R

Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h
(Table 4).

PE_INT

0

R

Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register
R02h/R03h (Table 4).

Table 5. Interrupt Register

ADDRESS = 01h

SYMBOL

BIT

R/W

DESCRIPTION

MASK7

7

R/W

Interrupt mask bit 7. A logic high enables the SUP_FLT interrupts. A logic low disables the SUP_FLT
interrupts.

MASK6

6

R/W

Interrupt mask bit 6. A logic high enables the TSTR_FLT interrupts. A low disables the TSTR_FLT
interrupts.

MASK5

5

R/W

Interrupt mask bit 5. A logic high enables the IMAX_FLT interrupts. A logic low disables the
IMAX_FLT interrupts.

MASK4

4

R/W

Interrupt mask bit 4. A logic high enables the CL_END interrupts. A logic low disables the CL_END
interrupts.

MASK3

3

R/W

Interrupt mask bit 3. A logic high enables the DET_END interrupts. A logic low disables the
DET_END interrupts.

MASK2

2

R/W

Interrupt mask bit 2. A logic high enables the LD_DISC interrupts. A logic low disables the LD_DISC
interrupts.

MASK1

1

R/W

Interrupt mask bit 1. A logic high enables the PG_INT interrupts. A logic low disables the PG_INT
interrupts.

MASK0

0

R/W

Interrupt mask bit 0. A logic high enables the PEN_INT interrupts. A logic low disables the PEN_INT
interrupts.

Table 6. Interrupt Mask Register