Rainbow Electronics MAX5066 - Manual (Page 21)

MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 21
Calculate C CFF such that:
where C CFF is C11 and C13 in Figure 6.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low loss-
es, low output noise, and clean and stable operation.
This is especially true for dual-phase converters where
one channel can affect the other. Use the following
guidelines for PC board layout:
1) Place the V DD , REG, and the BST1 and BST2
bypass capacitors close to the MAX5066.
2) Minimize all high-current switching loops.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz or higher) to enhance
efficiency and minimize trace inductance and
resistance.
4) Run the current-sense lines CSP_ and CSN_ very
close to each other to minimize loop areas. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
5) Place the bank of output capacitors close to the
load.
6) Isolate the power components on the top side from
the analog components on the bottom side with a
ground plane in between.
7) Provide enough copper area around the switching
MOSFETs, inductors, and sense resistors to aid in
thermal dissipation and reducing resistance.
8) Distribute the power components evenly across the
top side for proper heat dissipation.
9) Keep AGND and PGND isolated and connect them
at one single point close to the IC. Do not connect
them together anywhere else.
10) Place all input bypass capacitors for each input as
close to each other as is practical.
C
f R
CFF
C CF
=
Ч Ч Ч Ч
1
2 10 π
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EN
BST2
DH2
LX2
DL2
PGND
EN
IN
REG
V DD
DL1
LX1
DH1
BST1
CSN1
CSP1
EAOUT1
EAN1
CLP1
MODE
AGND
RT/CLKIN
REF
CLP2
EAN2
EAOUT2
CSP2
CSN2
TSSOP
TOP VIEW
MAX5066
*EXPOSED PADDLE
*CONNECT EXPOSED PAD TO GROUND PLANE.
Pin Configuration
Chip Information
TRANSISTOR COUNT: 6252
PROCESS: BiCMOS