Rainbow Electronics MAX5066 User Manual
Page 13
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
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13
The outer voltage control loop consists of the voltage-
error amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive volt-
age-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
Peak-Current Comparator
The peak-current comparator (see Figure 3) monitors
the voltage across the current-sense resistor (R
SENSE
)
and provides a fast cycle-by-cycle current limit with a
threshold of 52.5mV. Note that the average current-limit
threshold of 22.5mV still limits the output current during
short-circuit conditions. To prevent inductor saturation,
select an output inductor with a saturation current
specification greater than the average current limit of
22.5mV/R
SENSE
. Proper inductor selection ensures that
only extreme conditions trip the peak-current compara-
tor, such as a damaged output inductor. The typical
propagation delay of the peak current-limit comparator
is 260ns.
Current-Error Amplifier
The MAX5066 has two dedicated transconductance
current-error amplifiers CEA1 and CEA2 with a typical
g
M
of 550µS and 320µA output sink and source capabil-
ity. The current-error amplifier outputs (CLP1 and CLP2)
serve as the inverting input to the PWM comparators.
CLP1 and CLP2 are externally accessible to provide fre-
quency compensation for the inner current loops (see
C
CFF
, C
CF
, and R
CF
in Figure 2). Compensate the cur-
rent-error amplifier such that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the current-
error amplifier output to a 2V
P-P
ramp. At the start of
each clock cycle an R-S flip-flop resets and the high-
side drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminat-
ing the on cycle.
Voltage Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
-0.234V relative to V
CM
= 0.61V. Set the MAX5066 out-
put voltage by connecting a voltage-divider from the
output to EAN_ to GND (see Figure 4). At no load the
output of the voltage error amplifier is zero.
Use the equation below to calculate the no load voltage:
The voltage at full load is given by:
where
∆V
OUT
is the voltage-positioning window
described in the Adaptive Voltage Positioning section.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning (Figure 5) reduces the total number of out-
put capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
The internal 0.61V reference in the MAX5066 has a toler-
ance of ±0.9%. If we use 0.1% resistors for R
1
and R
2
,
we still have another 4% available for the variation in the
output voltage from nominal. This available voltage
range allows us to reduce the total number of output
capacitors to meet a given transient response require-
ment. This results in a voltage-positioning window as
shown in Figure 5.
From the allowable voltage-positioning window we can
calculate the value of R
F
from the equation below.
where
∆V
OUT
is the allowable voltage-positioning win-
dow, R
SENSE
is the sense resistor, 36 is the current-
sense amplifier gain, and R
1
is as shown in Figure 4.
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side dri-
vers (DL1 and DL2) drive the gates of external n-channel
MOSFETs. The high-peak sink and source current capa-
R
I
R
R
V
F
OUT
SENSE
OUT
=
Ч
Ч
Ч
36
1
∆
V
R
R
V
OUT FL
OUT
(
)
.
=
×
+
−
0 6135
1
1
2
∆
V
R
R
OUT NL
(
)
.
=
Ч
+
0 6135
1
1
2