Rainbow Electronics ADC12062 - Manual (Page 15)

Applications Information
(Continued)
Since the current flowing through the SENSE lines is essen-
tially zero there is negligible voltage drop across R
S and the
1 kX resistor so the voltage at the inverting input of the op
amp accurately represents the voltage at the top (or bot-
tom) of the ladder The op amp drives the FORCE input and
forces the voltage at the ends of the ladder to equal the
voltage at the op amps’s non-inverting input plus or minus
its input offset voltage For this reason op amps with low
V
OS
such as the LM627 or LM607 should be used for this
application When used in this configuration the ADC12062
typically has less than 0 5 LSB of offset and gain error with-
out any user adjustments
The 0 1 mF and 10 mF capacitors on the force inputs pro-
vide high frequency decoupling of the reference ladder The
500X force resistors isolate the op amps from this large
capacitive load The 0 01 mF 1 kX network provides zero
phase shift at high frequencies to ensure stability Note that
the op amp supplies in this example must be
g 10V to
g 15V to meet the input output voltage range requirements
of the LM627 and supply the sub-zero voltage to the
V
REF b (FORCE) pin The V REF 16 output should be by-
passed to analog ground with a 0 1 mF ceramic capacitor
The reference inputs are fully differential and define the
zero to full-scale range of the input signal They can be
configured to span up to 5V (V
REF b
e 0V V REF a
e 5V)
or they can be connected to different voltages (within the
0V to 5V limits) when other input spans are required The
ADC12062 is tested at V
REF b (SENSE) e 0V V
REF a
(SENSE) e 4 096V Reducing the reference voltage span to
less than 4V increases the sensitivity (reduces the LSB size)
of the converter however noise performance degrades
when lower reference voltages are used A plot of dynamic
performance vs reference voltage is given in the Typical
Performance Characteristics section
If the converter will be used in an application where DC
accuracy is secondary to dynamic performance then a sim-
pler reference circuit may suffice The circuit shown in
Fig-
ure 11 will introduce several LSBs of offset and gain error
but INL DNL and all dynamic specifications will be unaf-
fected
All bypass capacitors should be located as close to the
ADC12062 as possible to minimize noise on the reference
ladder The V
REF 16 output should be bypassed to analog
ground with a 0 1 mF ceramic capacitor
The LM4040 shunt voltage reference is available with a
4 096V output voltage With initial accuracies as low as
g 0 1% it makes an excellent reference for the ADC12062
TL H 11490 – 21
FIGURE 11 Using the V
REF
Force Pins Only
15