Rainbow Electronics MAXQ7667 - Manual (Page 24)

MAXQ7667
16-Bit, RISC, Microcontroller-Based,
Ultrasonic Distance-Measuring System
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The following four digital I/Os form the TAP interface:
• TDO—Serial output signal for test instruction and
data. Data transitions on the falling edge of TCK.
TDO idles high when inactive. TDO serially trans-
fers internal data to the external host. Data trans-
fers lease significant bit first.
• TDI—Serial input signal for test instruction and
data. Transition data on the rising edge of TCK.
TDO pulls high when unconnected. TDI serially
transfers data from the external host to the internal
TAP module shift registers. Data transfers least
significant bit first.
• TCK—Serial clock for the test logic. When TCK
stops at 0, storage elements in the test logic must
retain their data indefinitely. Force TCK high when
inactive.
• TMS—Test mode selection. The rising edge of TCK
samples the test signals at TMS. The TAP controller
decodes the test signals at TMS to control the test
operation. Force TMS high when inactive.
UART/LIN Interface
The MAXQ7667 includes a UART/LIN transceiver com-
bination that supports communication speeds up
2MBd. The LIN standard for example limits communica-
tion speed to 20kBd or less. Connect a LIN transceiver
or other UART connections such as RS-232 and RS-485
directly to the MAXQ7667’s 2-wire interface: URX and
UTX. The MAXQ7667 operates as a LIN slave or LIN
master device. The UART provides the programmable
baud-rate generators to communicate effectively to or
from the LIN transceiver. The device holds up to 8
bytes of data in each of the transmit and receive FIFOs.
The following characteristics apply to the MAXQ7667
UART/LIN interface:
• Full-duplex operation for asynchronous data trans-
fers up to 500kBd (system clock/32)
• Half-duplex operation for synchronous data trans-
fers up to 2MBd (system clock/8)
• 8-deep receive and transmit FIFO with program-
mable interrupt for receive and transmit
• Independent baud-rate generator
• Programmable 9th data bit (commonly used for
parity or address/data selection)—UART mode
only
• Hardware support for LIN including break detec-
tion, autobaud, address identity filtering, check-
sum calculation, and block length checking
• Supports common RS-232 and LIN baud rates:
1000, 1200, 2400, 4800, 9600, 19,200, 20,000,
38,400, 57,600, and 115,200 with system clock =
16MHz.
SPI Interface
The MAXQ7667 supports 4-wire SPI interface communi-
cation with 8-bit or 16-bit data streams operating in
either master mode or slave mode. The SPI interface
allows synchronous half-duplex or full-duplex serial
data transfers to a wide variety of external serial
devices using MISO, MOSI, SS, and SCLK signals.
Collision detection is provided when two or more mas-
ters attempt a data transfer at the same time. See
Section 9 of the
MAXQ7667 User’s Guide .
General-Purpose Digital I/O Ports
Two 8-bit digital I/O ports (P0._ and P1._), with dedicat-
ed one or more alternative functions, are available as
general-purpose I/Os (GPIOs) under the control of the
integrated MAXQ20. Set each I/O within each port indi-
vidually as an input or output. The GPIOs incorporate a
Schmitt trigger receiver and a full CMOS output driver
(Figure 13). Each GPIO configures as an input with
pullup to DVDDIO at power-up. When programmed as
an input, each I/O is configurable for high-impedance,
weak pullup to DVDDIO or pulldown to DGND. When
programmed as an output, writing to the port output
register (PO) controls the output logic state. The out-
puts source or sink at least 1.6mA. Configure the drive
strength for each I/O within each port to high or low
using the pad drive strength register for optimum EMI
performance. All the I/O ports have interrupt capability
that wake up the device while in stop mode and have
protection circuitry to DVDDIO and DGND.
Supply-Voltage Regulators
The MAXQ7667 requires three different power-supply
voltages. DVDDIO, nominally +5V, allows interfacing to
standard 5V logic on all the digital I/Os including the
LIN/UART, JTAG, and SPI ports. DVDD, nominally
+2.5V, powers all the high-speed digital circuits. AVDD,
nominally 3.3V, powers the analog circuits.
External power supplies or internal voltage regulators
provide each of the supply voltages. The internal volt-
age regulators provide 3.3V and 2.5V supplies from the
5V DVDDIO input. Obtain the 5V supply from a higher
external voltage supply by using a few external compo-
nents. The MAXQ7667 includes an internal error ampli-
fier used to regulate the voltage on DVDDIO by driving
the gate or base of an external pass transistor. Refer to
the
MAXQ7667 User’s Guide for more details on the
external components needed for 5V regulation.