I2c bus controller timing, C bus controller timing – Rainbow Electronics MAXQ2010 User Manual
Page 11
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MAXQ2010
16-Bit Mixed-Signal Microcontroller with LCD
______________________________________________________________________________________
11
I
2
C BUS CONTROLLER TIMING
(V
DVDD
= V
AVDD
= 2.7V to 3.6V, T
A
= -40°C to +85°C.) (Note 22) (Figure 4)
STANDARD MODE
FAST MODE
PARAMETER SYMBOL
MIN MAX MIN MAX
UNITS
Operating Frequency
f
I2C
0 100 0 400
kHz
Hold Time After (Repeated)
START
t
HD:STA
4.0 0.6
μs
Clock Low Period
t
LOW_I2C
4.7 1.3
μs
Clock High Period
t
HIGH_I2C
4.0 0.6
μs
Setup Time for Repeated START
t
SU:STA
4.7 0.6
μs
Hold Time for Data
t
HD:DAT
0
(Note 23)
3.45
(Note 24)
0
(Note 23)
0.9
(Note 24)
μs
Setup Time for Data
t
SU:DAT
250
100
(Note 25)
ns
SDA/SCL Fall Time
t
F_I2C
300
20 + 0.1C
B
(Note 26)
300 ns
SDA/SCL Rise Time
t
R_I2C
1000
20 + 0.1C
B
(Note 26)
300 ns
Setup Time for STOP
t
SU:STO
4.0 0.6
μs
Bus-Free Time Between STOP
and START
t
BUF
4.7 1.3
μs
Capacitive Load for Each Bus
Line
C
B
400 400
pF
Noise Margin at the Low Level
for Each Connected Device
(Including Hysteresis)
V
NL_I2C
0.1
x
V
DVDD
0.1
x
V
DVDD
V
Noise Margin at the High Level
for Each Connected Device
(Including Hysteresis)
V
NH_I2C
0.2
x
V
DVDD
0.2
x
V
DVDD
V
Note 22: All values referenced to V
IH_I2C(MIN)
and V
IL_I2C(MAX)
.
Note 23: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IH_I2C(MIN)
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 24: The maximum t
HD:DAT
need only be met if the device does not stretch the low period (t
LOW_I2C
) of the SCL signal.
Note 25: A fast-mode I
2
C bus device can be used in a standard-mode I
2
C bus system, but the requirement t
SU:DAT
≥ 250ns must
be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R_I2C(MAX)
+ t
SU:DAT
= 1000 + 250
= 1250ns (according to the standard-mode I
2
C specification) before the SCL line is released.
Note 26: C
B
—Total capacitance of one bus line in pF.