Rainbow Electronics MAX8707 - Manual (Page 33)

MAX8707
Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
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Disable voltage positioning by shorting VPS directly to FBS.
Transient Droop
Connect a resistor (R TRC ) between TRC and REF to set
the transient droop (R
DROOP(AC)
) based on the voltage-
positioning requirements. TRC allows the controller to
quickly respond to load transients, but it does not affect
the DC steady-state droop. Choose R
TRC based on the
equation:
where R CS is the current-sense element connected from
CSP_ to CSN_ (which is typically the inductor’s effective
DCR: R
CS = L / R EQ C SENSE ), R TRANS is the current-
sense amplifier gain divided by the transient amplifier’s
transconductance as defined in the Electrical Character-
istics
table , and R DROOP(AC) is typically 80% of the DC
voltage-positioning slope to minimize the transient
sag voltage.
The TRC resistance also sets the small-signal loop gain,
so a maximum R
TRC value is required for stability, even
if voltage positioning is not used (VPS = FBS).
V RIPPLE R TRC < (R TRANS R SENSE
∆I
L ) / 3
TRC is high impedance in shutdown.
Applications Information
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by stability requirements, not the minimum
off-time (t
OFF(MIN)
). The MAX8707 does not include
slope compensation, so the controller becomes unsta-
ble with duty cycles greater than 50% per phase:
V
IN(MIN)
≥ 2V
OUT(MAX)
However, the controller may briefly operate with duty
cycles over 50% during heavy load transients.
Maximum Input Voltage
The MAX8707 controller and driver has a minimum on-
time, which determines the maximum input operating
voltage that maintains the selected switching frequen-
cy. With higher input voltages, each pulse delivers
more energy than the output is sourcing to the load. At
the beginning of each cycle, if the output voltage is still
above the feedback threshold voltage, the controller
does not trigger an on-time pulse resulting in pulse-
skipping operation regardless of the operating mode
selected by SKIP. This allows the controller to maintain
regulation above the maximum input voltage, but forces
the controller to effectively operate with a lower switch-
ing frequency. This results in an input threshold voltage
at which the controller begins to skip pulses (V
IN(SKIP) ):
where f
SW
is the switching frequency per phase select-
ed by OSC, and t
ON(MIN)
is 110ns plus the driver’s
turn-off delay (PWM low to LX low) minus the driver’s
turn-on delay (PWM high to LX high). For the best high-
voltage performance, use the slowest switching-fre-
quency setting (200kHz per phase, OSC = GND).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(
Figure 9). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
2) Connect all analog grounds to a separate solid cop-
per plane, which connects to the GND pin of the
controller. This includes the V
CC bypass capacitor,
REF and GNDS bypass capacitors, compensation
(CCV, TRC) components, and the resistive dividers
connected to I
LIM(AVE) , SUSV, and OFS.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single m
Ω of excess trace resistance caus-
es a measurable efficiency penalty.
4) Connections for current limiting (CSP_, CSN_) and
voltage positioning (CRSP, CRSN) must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy.
5) Route high-speed switching nodes and driver traces
away from sensitive analog areas (REF, CCV, TRC,
VPS, etc.). Make all pin-strap control input connec-
tions (SHDN, SKIP, SUS, OSC) to analog ground or
V
CC rather than power ground or V DD .
6) Keep the drivers close to the MOSFET, with the
gate-drive traces (DL, DH, LX, and BST) short and
wide to minimize trace resistance and inductance.
V V
f t
IN SKIP OUT
SW ON MIN
( )
( )
=






1
R
R R
R
TRC
TRANS CS
PH DROOP AC
=
η
( )