Texas Instruments THUNDERSWITCH II TNETX4090 - Manual (Page 12)

TNETX4090
ThunderSWITCH II

9-PORT 100-/1000-MBIT/S ETHERNET

SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
12
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)
TERMINAL
I/O
INTERNAL
DESCRIPTION
NAME NO.
I/O
RESISTOR
DESCRIPTION
M00_RENEG
M01_RENEG
M02_RENEG
M03_RENEG
M04_RENEG
M05_RENEG
M06_RENEG C26
D26
D1
C1
F3
F2
AA3
O None
Renegotiate. Indicates to the attached PHY device that this port wishes to renegotiate a new
configuration.
M00_RXDV
M01_RXDV
M02_RXDV
M03_RXDV
M04_RXDV
M05_RXDV
M06_RXDV
M07_RXDV D19
A16
C9
C4
J2
T4
W1
AC8
I Pulldown
Receive data valid. Indicates data on Mxx_RXD7–Mxx_RxD0. is valid. This signal is
synchronous to Mxx_RCLK.
M00_RXD3
M00_RXD2
M00_RXD1
M00_RXD0
M01_RXD3
M01_RXD2
M01_RXD1
M01_RXD0
M02_RXD3
M02_RXD2
M02_RXD1
M02_RXD0
M03_RXD3
M03_RXD2
M03_RXD1
M03_RXD0
M04_RXD3
M04_RXD2
M04_RXD1
M04_RXD0
M05_RXD3
M05_RXD2
M05_RXD1
M05_RXD0
M06_RXD3
M06_RXD2
M06_RXD1
M06_RXD0
M07_RXD3
M07_RXD2
M07_RXD1
M07_RXD0 D20
C20
B20
A20
D15
C15
B15
A15
D10
C10
B10
A10
D5
C5
B5
A5
K3
K2
K1
J1
R4
R3
R2
R1
Y4
Y3
Y2
Y1
AC7
AD7
AE7
AF7
I Pullup
Receive data. Nibble receive data from the attached PHY device. Data on these signals is
synchronous to Mxx_RCLK. When Mxx_RXDV and Mxx_RXER are low, these terminals are
sampled the cycle before Mxx_LINK goes high to configure the port, based on capabilities
negotiated by the attached PHY device as follows:
– Mxx_RXD0 indicates full-duplex mode when high; half duplex when low, and sets
duplex in PortxStatus.
– Mxx_RXD1 indicates IEEE Std 802.3 pause frame support when high; no pause
when low, and sets pause in PortxStatus.
– Mxx_RXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, and sets speed in
PortxStatus.
– Mxx_RXD3 is unused and is ignored.