Texas Instruments TMS320DM643X DMP - Manual (Page 5)

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List of Tables
1 UART Supported Features/Characteristics by Instance ............................................................... 8
2 Baud Rate Examples for 27 MHz UART Input Clock
.................................................................
11
3 UART Signal Descriptions
................................................................................................
12
4 Character Time for Word Lengths ....................................................................................... 15
5 UART Interrupt Requests Descriptions ................................................................................. 19
6 UART Registers ........................................................................................................... 21
7 Receiver Buffer Register (RBR) Field Descriptions
...................................................................
22
8 Transmitter Holding Register (THR) Field Descriptions
..............................................................
23
9 Interrupt Enable Register (IER) Field Descriptions ................................................................... 24
10 Interrupt Identification Register (IIR) Field Descriptions .............................................................. 25
11 Interrupt Identification and Interrupt Clearing Information ............................................................ 26
12 FIFO Control Register (FCR) Field Descriptions
......................................................................
27
13 Line Control Register (LCR) Field Descriptions
.......................................................................
28
14 Relationship Between ST, EPS, and PEN Bits in LCR ............................................................... 29
15 Number of STOP Bits Generated ....................................................................................... 29
16 Modem Control Register (MCR) Field Descriptions ................................................................... 30
17 Line Status Register (LSR) Field Descriptions
........................................................................
31
18 Divisor LSB Latch (DLL) Field Descriptions
............................................................................
34
19 Divisor MSB Latch (DLH) Field Descriptions .......................................................................... 34
20 Peripheral Identification Register 1 (PID1) Field Descriptions ....................................................... 35
21 Peripheral Identification Register 2 (PID2) Field Descriptions ....................................................... 35
22 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
...........................
36
23 Document Revision History
..............................................................................................
37
5 SPRU997C – December 2009 List of Tables
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