Texas Instruments TMS320DM643X DMP User Manual
Page 3

Preface
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1
Introduction
........................................................................................................................
1.1
Purpose of the Peripheral
..............................................................................................
1.2
Features
..................................................................................................................
1.3
Functional Block Diagram
..............................................................................................
1.4
Industry Standard(s) Compliance Statement
........................................................................
2
Peripheral Architecture
......................................................................................................
2.1
Clock Generation and Control
........................................................................................
2.2
Signal Descriptions
....................................................................................................
2.3
Pin Multiplexing
........................................................................................................
2.4
Protocol Description
...................................................................................................
2.5
Endianness Considerations
..........................................................................................
2.6
Operation
................................................................................................................
2.7
Reset Considerations
..................................................................................................
2.8
Initialization
.............................................................................................................
2.9
Interrupt Support
.......................................................................................................
2.10
DMA Event Support
...................................................................................................
2.11
Power Management
...................................................................................................
2.12
Emulation Considerations
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2.13
Exception Processing
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3
Registers
..........................................................................................................................
3.1
Receiver Buffer Register (RBR)
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3.2
Transmitter Holding Register (THR)
.................................................................................
3.3
Interrupt Enable Register (IER)
......................................................................................
3.4
Interrupt Identification Register (IIR)
................................................................................
3.5
FIFO Control Register (FCR)
.........................................................................................
3.6
Line Control Register (LCR)
..........................................................................................
3.7
Modem Control Register (MCR)
.....................................................................................
3.8
Line Status Register (LSR)
...........................................................................................
3.9
Divisor Latches (DLL and DLH)
......................................................................................
3.10
Peripheral Identification Registers (PID1 and PID2)
..............................................................
3.11
Power and Emulation Management Register (PWREMU_MGMT)
..............................................
Appendix A Revision History
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3
SPRU997C – December 2009
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