Texas Instruments TMS320DM643X DMP User Manual
Page 4

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List of Figures
1
UART Block Diagram
.......................................................................................................
2
UART Clock Generation Diagram
.......................................................................................
3
Relationships Between Data Bit, BCLK, and UART Input Clock
....................................................
4
UART Protocol Formats
..................................................................................................
5
UART Interface Using Autoflow Diagram
..............................................................................
6
Autoflow Functional Timing Waveforms for RTS
......................................................................
7
Autoflow Functional Timing Waveforms for CTS
......................................................................
8
UART Interrupt Request Enable Paths
.................................................................................
9
Receiver Buffer Register (RBR)
.........................................................................................
10
Transmitter Holding Register (THR)
....................................................................................
11
Interrupt Enable Register (IER)
..........................................................................................
12
Interrupt Identification Register (IIR)
....................................................................................
13
FIFO Control Register (FCR)
............................................................................................
14
Line Control Register (LCR)
.............................................................................................
15
Modem Control Register (MCR)
.........................................................................................
16
Line Status Register (LSR)
...............................................................................................
17
Divisor LSB Latch (DLL)
..................................................................................................
18
Divisor MSB Latch (DLH)
.................................................................................................
19
Peripheral Identification Register 1 (PID1)
.............................................................................
20
Peripheral Identification Register 2 (PID2)
.............................................................................
21
Power and Emulation Management Register (PWREMU_MGMT)
.................................................
4
List of Figures
SPRU997C – December 2009
Copyright © 2009, Texas Instruments Incorporated