Texas Instruments TMS320C674X - Manual (Page 5)

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5.31 Emulation Control Register (EMCONTROL) ...................................................................... 114
5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 114
5.33 MAC Configuration Register (MACCONFIG)
.....................................................................
115
5.34 Soft Reset Register (SOFTRESET)
................................................................................
115
5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) .............................................. 116
5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 116
5.37 MAC Hash Address Register 1 (MACHASH1) ................................................................... 117
5.38 MAC Hash Address Register 2 (MACHASH2)
...................................................................
117
5.39 Back Off Test Register (BOFFTEST)
..............................................................................
118
5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ....................................................... 118
5.41 Receive Pause Timer Register (RXPAUSE) ...................................................................... 119
5.42 Transmit Pause Timer Register (TXPAUSE) ..................................................................... 119
5.43 MAC Address Low Bytes Register (MACADDRLO)
.............................................................
120
5.44 MAC Address High Bytes Register (MACADDRHI)
.............................................................
121
5.45 MAC Index Register (MACINDEX) ................................................................................. 121
5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) ........................... 122
5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) ........................... 122
5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)
............................................
123
5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP)
............................................
123
5.50 Network Statistics Registers
........................................................................................
124
Appendix A Glossary ............................................................................................................... 133
Appendix B Revision History ..................................................................................................... 135
5 SPRUFL5B – April 2011 Contents
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