Texas Instruments TMS320C674X - Manual (Page 47)

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2.12 Receive and Transmit Latency
The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of a
packet on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or a
complete packet, are available in the FIFO.
Transmit underrun cannot occur for packet sizes of TXCELLTHRESH times 64 bytes (or less). For larger
packet sizes, transmit underrun occurs if the memory latency is greater than the time required to transmit
a 64-byte cell on the wire; this is 5.12
μ s in 100 Mbps mode and 51.2 μ s in 10 Mbps mode. The memory
latency time includes all buffer descriptor reads for the entire cell data.
Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a
64-byte cell on the wire: 5.12
μ s in 100 Mbps mode, or 51.2 μ s in 10 Mbps mode. The latency time
includes any required buffer descriptor reads for the cell data.
Latency to system’s internal and external RAM can be controlled through the use of the transfer node
priority allocation register available at the device level. Latency to descriptor RAM is low because RAM is
local to the EMAC, as it is part of the EMAC control module.
2.13 Transfer Node Priority
The device contains a chip-level master priority register that is used to set the priority of the transfer node
used in issuing memory transfer requests to system memory.
Although the EMAC has internal FIFOs to help alleviate memory transfer arbitration problems, the average
transfer rate of data read and written by the EMAC to internal or external processor memory must be at
least that of the Ethernet wire rate. In addition, the internal FIFO system can not withstand a single
memory latency event greater than the time it takes to fill or empty a TXCELLTHRESH number of internal
64 byte FIFO cells.
For 100 Mbps operation, these restrictions translate into the following rules:
•
The short-term average, each 64-byte memory read/write request from the EMAC must be serviced in
no more than 5.12
μ s.
• Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μ s.
47 SPRUFL5B – April 2011 EMAC/MDIO Module
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