Ricoh R5C841 - Manual (Page 40)

R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard Data Sheet
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4.16 1394 OHCI
The 1394 OHCI block in the R5C841 employs DMA engines for high-performance data transfer,
host bus interface and FIFO. The R5C841 supports two types of data transfer: asynchronous and
isochronous. Prefer to the 1394 OHCI release 1.1/1.0 specifications for settings and procedures
of the controller.
4.16.1 Asynchronous Functions
The R5C841 supports all of transmission and reception defined in 1394 packet formats.
Transmitted packets are read out of host memory and received packets are written into host
memory, both using DMA. And the R5C841 can be programmed as a bus bridge between the
host bus and the 1394 interface by the direct execution of the 1394 read/write requests to the
host bus memory space.
4.16.2 Isochronous Functions
The R5C841 includes the cycle master function as defined in the 1394 specification. The cycle
start packet is transferred at intervals of 8KHz cycle clock. This cycle master uses the internal
cycle clock. When the R5C841 is not the cycle master, the R5C841 can sustain its internal cycle
timer sychronized with the cycle master node by correcting its own cycle timer with the reload
value from the cycle start packet. The R5C841 supports each DMA controller for each
isochronous transmit and isochronous receive. Each DMA controller supports 4 different DMA
contexts.
4.16.3 DMA
The R5C841 supports seven types of DMA. Each type of DMA has register space and data
stream referred to as a DMA context.
DMA Type Number of Contexts
Asynchronous Transmit Request x 1, Response x 1
Asynchronous Receive Request x 1, Response x 1
Isochronous Transmit X 4
Isochronous Receive X 4
Self-ID Receive X 1
Physical Request & Physical Response No Context
Each asynchronous and isochronous context is composed of buffer descriptor lists called a DMA
context program, which is stored in main memory. The DMA controller finds the necessary data
buffers through the DMA context programs.
The Self-ID receive controller is controlled not by the DMA context program but by the two other
registers. The R5C841 supports the Physical Request DMA and the Physical Response DMA
controllers in order to transmit the receive request, which is to read and write directly to the bus
memory space. These controllers are also controlled not by the DMA context program but by the
other reserved register.