Ricoh R5C841 - Manual (Page 30)

R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard Data Sheet
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4.7 Interrupts
The R5C841 supports PCI interrupt signals INTA#, INTB# and INTC# as well as ISA interrupt
signals IRQx. They transmit to the system the Card Status Change Interrupt as a card
insert/remove event, the Function Interrupt by the PC card, the DMA Interrupt and the Device
Interrupt defined on 1394 OHCI, and interrupts defined on SD Card/Memory Stick/xD Picture
Card interface. INTA# is assigned to the PC Card interface, INTB# is assigned to the 1394 OHCI
and INTC# is assingned to the SD Card/Memory Stick/xD Picture Card interface. Interrupts of the
PC Card interface and the 1394 can be reassigned by the INT Select bits (bit1, 0) of the 1394
Misc Control 2 register, and Interrupts of SD Card/Memory Stick/xD Picture Card interface can be
reassigned by the INT Select bits (bit26, 25) of the SD Misc Control register / the MS Misc Control
register/the xD Misc Control register.
INT Select INT Select
bit1 bit0 PC Card 1394 bit26 bit25 SD/MS/xD
0 0 INTA# INTB# 0 0 Reserved
0 1 INTA# INTB# 0 1 INTC#
1 0 INTA# INTA# 1 0 INTB#
1 1 INTA# INTA# 1 1 INTA#
On the PC Card, setting the IRQ-ISA Enable bit of the Bridge Control register enables the IRQx
routing register for PC Card-16/32. On the other hand, setting CINT-ISA Disable bit (Config.A0h
bit6) disables the 32bit Function Interrupt to route into the ISA Interrupt and enables to route into
the INT Interrupt. And also, setting the Card Status Change Interrupt Configuration register on the
16bit Control registers the 16bit Card Status Change Interrupt to route into the ISA Interrupt. But,
the R5C841 doesn’t support IRQ-ISA function on 1394 OHCI.
On the 1394 OHCI, the R5C841 transmits interrupt signals to the host on the end of the DMA
transaction, and also transmits interrupts of the LINK layer and the PHY layer. The IntEvent
register and the IntMask register in the OHCI registers control these interrupts. The IntEvent
register is used to indicate generations of an interrupt event and the IntMask register is used to
enable the selected interrupt. Writing into the IntEventClear by software enables to clear the
interrupt.
On the SD Card interface, the Memory Stick interface and the xD Picture Card interface, the
R5C841 can inform a card insert/remove event or an error as an interrupt to the system. PCI
interrupt signals are open drain outputs. When ISA-IRQ mode is enabled, IRQx signals are
programmable to either positive edge mode or level mode. RI_OUT# can be reassigned to an
interrupt signal such as Remote Wakeup signal.
In addition to primary interrupt functions, the R5C841 supports Serialized IRQ. When SRIRQ
Enable bit (bit 7) of the PC Card Misc Control register is set to ‘1b’, UDIO0 works as SRIRQ#
(default). And GPIO and LED0# are also enabled. SRIRQ# output enables a Wired-OR structure
that simply transfer a state of one or more device’s IRQ to the host controller. Both of a device
and a host controller enables a transferring start.
A transferring, called an IRQSER Cycle, consists of three frame types: one Start Frame, several
IRQ/Data Frames, and one Stop Frame. When the SR_PCI_INT_Disable bit (bit5) of the PC Card
Misc control register is ‘Low’, frames of INTA#, INTB#, INTC# and INTD# (PCI Interrupt signals)
are output following IOCHK# frame are output. When it is ‘High’, IRQx only are output from
SRIRQ#.
All cycle uses PCICLK as its clock source. The IRQSER Start Frame has two operation modes:
Quiet (Active) mode and Continuous (Idle) mode. On the Quiet (Active) mode, any device can
initiate a Start Frame. By occurring of interruptive requests, the R5C841 outputs 1-pulse of
PCICLK (Low) and Serialized IRQ is kept on Hi-Z during the rest of a Start Frame. After that,
IRQ/DATA Frame follows.
In Continuous (Idle) mode, only Host Controller can initiate a Start Frame. The R5C841 becomes
waiting state to detect 4-8 PCICLK of Start Pulse. These modes change automatically by
monitoring the Stop pulse width in a Stop Frame. Quiet (Active) mode is repeated when width of
Stop Pulse is 2PCICLK, and Continuous (Idle) mode is repeated when it is 3PCICLK. After
assertion of the GBRST#, the default is Continuous (Idle) mode.
Timing of the Start Frame and the Stop Frame is as follows.