Ricoh R5C841 - Manual (Page 29)

R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard Data Sheet
12345  2004 R EV .1.10 4-4
4.5 Data Buffers, Posting Write, Prefetching Read
The R5C841 provides data buffers, address buffers, and command buffers in order to maintain a
high-speed data transfer between the PCI bus and the CardBus. The transaction from the PCI
bus to the CardBus allows 8-DWORD buffers of Posting Write Data and Prefetching Read Data.
Conversely, the transaction from the CardBus to the PCI bus allows 12-DWORD buffers of
Posting Write Data and Prefetching Read Data. Posting of write data is permitted a master to end
writing data before a target’s end of writing data. The transactions that cross the R5C841 in either
direction enable a high-speed transfer.
The R5C841 provides a high-speed data transfer by PCI burst transfers when Prefetching Read
Data or Posting Write Data is implemented on the PCI bus and the 1394 bus. Accesses to the SD
Card, the Memory Stick and the xD Picture Card do not support the PCI burst transfers.
4.6 Error Support
4.6.1 Parity Error
The R5C841 provides the parity generation and the parity error detection on both the primary PCI
bus and the secondary CardBus. Having detected an address parity error, the R5C841 asserts
SERR# and sets the Detected Parity Error bit in the PCI Status register. Having detected a data
parity error, the R5C841 asserts PERR# and sets the Detected Parity Error bit in the PCI Status
register. And also, having detected a data parity error, the R5C841 passes the bad data and bad
parity on to the opposite interface if possible. This enables the parity error recovery mechanisms
outlines in the PCI Local Bus Specification without special considerations for the presence of a
bridge in the path of the transaction.
4.6.2 Master Abort
Having the occurred master abort at the destination, the R5C841 implements one of two
transactions. One is a transaction that is compatible with ISA to invalidate data. (Returns all “1”
when read and invalidates the data when write.) The other way is to assert SERR#.
4.6.3 Target Abort
Having the occurred target abort at the destination, the R5C841 transmits errors as target abort to
the original master as thoroughly as possible. But, if cannot, the R5C841 asserts SERR# and
transmits errors to the system.
4.6.4 CardBus System Error
Having the asserted CSERR# on the secondary CardBus interface, the R5C841 always asserts
SERR# on the primary PCI interface and transmits errors to the system.
4.6.5 PCI Bus Error concerned with 1394 OHCI
On the 1394 OHCI function, the R5C841 provides occurred PCI Bus errors and some information
to recover the errors to system software, via the Context register or the descriptor.