NEC PD75P308 - Manual (Page 3)

µ
PD75P308
3
BLOCK DIAGRAM
P00-P03
P10-P13
P20-P23
P30-P33
/MD0-MD3
P40-P43
P50-P53
P60-P63
P70-P73
4
4
4
4
4
4
4
4
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
S0-S23
S24/BP0
-S31/BP7
COM0-COM3
V -V
LCO LC2
BIAS
LCDCL/P30
SYNC/P30
24
8
4
3
LCD
CONTROLLER
/DRIVER
f
LCD
RESET
SP(8)
BANK
GENERAL REG.
DATA
MEMORY
(RAM)
512 x 4 BITS
CY
ALU
V
SS
V
DD
V
PP
DECODE
AND
CONTROL
PROGRAM
MEMORY
(PROM)
8064 x 8 BITS
PROGRAM
COUNTER(13)
STAND BY
CONTROL
SYSTEM CLOCK
GENERATOR
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
SUB MAIN
f /2
X
N
X2 X1 XT2 XT1
PCL/P22
CPU
CLOCK
INTERRUPT
CONTROL
BIT SEQ.
BUFFER(16)
SERIAL
INTERFACE
WATCH
TIMER
TIMER/EVENT
COUNTER
#0
BASIC
INTERVAL
TIMER
TI0/P13
PTO0/P20
BUZ/P23
SI/SBI/P03
SO/SB0/P02
SCK/P01
INTBT
INTT0
INTW
INTCSI
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60-
KR3/P63,
KR4/P70-
KR7/P73
8
f
LCD