NEC SP B-Series - Manual (Page 17)

1-6 Technical Information
The system supports the following DIMM configurations:
T 4-Mbit by 64 (32-MB DIMM)
T 8-Mbit by 64 (64-MB DIMM)
T 16-Mbit by 64 (128-MB DIMM).
Chipset
The Intel 440BX chipset provides DMA, memory, and bus control. The chipset
includes the following chips:
T Intel 82443BX PCI/AGP (PAC)

provides bus-control signals, address
paths, and data paths for transfers between the processor’s host bus, PCI
bus, Accelerated Graphics Port (AGP), and main memory.
T Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E)

implements the
PCI-to-ISA bridge, PCI IDE functionality, Universal Serial Bus (USB)
host/hub functions, and enhanced power management.
PCI Local Bus
The 32-bit industry-standard PCI bus is a highly-integrated input/output (I/O)
interface that offers the highest performance local bus available for the Pentium
II processor. The PCI bus supports burst modes that send large chunks of data
across the bus, allowing fast displays of high-resolution images.
The high-bandwidth PCI local bus eliminates data bottlenecks found in
traditional systems, maintains maximum performance at high clock speeds, and
provides a clear upgrade path to future technologies.
The PCI bus contains two embedded PCI devices: the PCI local bus IDE
interface and the PCI video/graphics controller. The PCI bus also contains a
connector for attaching the bus expansion board.
Expansion Bus
The expansion bus contains one ISA slot, three PCI slots, one PCI/ISA slot, and
one AGP video slot. The PCI ISA IDE Xcelerator chip (PIIX4E) provides the
logic that enables the ISA bus functions. With 24-bit memory addressing, a
16-bit data path, and an 8-MHz clock, the ISA bus is designed to support all
peripherals compatible with the IBM
®
AT™ standard. For PCI functions, the
Xcelerator chip provides 32-bit memory addressing, 32-bit data path, and a
33-MHz clock speed.
BIOS
The BIOS (Basic Input Output System) is stored in the Flash EPROM. The
Flash EPROM is reprogrammable and allows fast, economical BIOS upgrades.
The system memory map is shown in the following table.