Patton electronic 3060/V24 - Manual (Page 18)

3060/V24
102001UA
A-2 A PPENDIX
P ATTON E LECTRONICS C O . I NSTALLATION A ND O PERATIONS M ANUAL
Master DTE / Sub-Channel DCE Interface Flow Diagram
Master DTE / Sub-Channel DTE Interface Flow Diagram
Master Port is a DTE
Pin 3 RXD Pin 2 TXD
Pin 2 TXD Pin 3 RXD
Pin 4 RTS
Pin 5 CTS
Pin 6 DSR
Pin 8 DCD
Pin 20 DTR
Pin 4 RTS
Pin 5 CTS
Pin 6 DSR
Pin 8 DCD
Pin 20 DTR
Switch Control
Buffer
+8v
Pin 15 TXC
Pin 17 RXC
Pin 24 ETXC
Pin 15 TXC
Pin 17 RXC
Pin 24 ETXC
Clk In Clk Out
Master RX Clock
Selection Logic
Master TX Clock
Selection Logic
Channel Port is a DTE
Pin 15 TXC
Pin 17 RXC
Pin 24 ETXC
Pin 15 TXC
Pin 17 RXC
Pin 24 ETXC
Master RX Clock
Selection Logic
Master TX Clock
Selection Logic
Master Port is a DTE
Pin 3 RXD Pin 3 RXD
Pin 2 TXD Pin 2 TXD
Pin 4 RTS
Pin 5 CTS
Pin 6 DSR
Pin 8 DCD
Pin 20 DTR
Pin 4 RTS
Pin 5 CTS
Pin 6 DSR
Pin 8 DCD
Pin 20 DTR
Switch Control
Channel Port is a DCE