PC Concepts SHG2 DP - Manual (Page 20)

Processor and Chipset Intel® SHG2 DP Server Board Technical Product Specification
Intel Order Number C11343-001 Revision 1.0 8
2.2.4 ServerWorks* Grand Champion* LE Chipset
The CMIC-LE, CIOB-X2, and CSB5 chips provide the pathway between processor and I/O
systems. The CMIC-LE is responsible for accepting access requests from the host (processor)
bus, and directing all I/O accesses to one of the PCI buses or legacy I/O locations. If the cycle
is directed to one of the 64-bit PCI segments, the CMIC-LE communicates with the CIOB-X2
through a private interface called the IMB bus.
If the cycle is directed to the 32-bit PCI segment
or to the CSB5, the cycle is output on the private interface between the CMIC-LE and the CSB5
called the Thin-IMB bus.
The CIOB-X2 translates the IMB bus operation to a 64-bit PCI-X
signaling environment, operating at 100 MHz or 133 MHz (PCI Local Bus Specification 2.2 and
PCI-X Specification 1.0a compliant).
The IMB bus consists of two data paths, one upstream (to the CMIC-LE from the CIOB-X2) and
one downstream (from the CMIC-LE to the CIOB-X2). The interface is 16 bits wide and
operates at 400 MHz with double-pumped data, providing over 1.6 GB per second of bandwidth
in each direction, or 3.2 GB per second of bandwidth in both directions concurrently.
All I/O for the SHG2 server board, including PCI-X, is directed through the CMIC-LE and then
through either the CIOB-X2 or the CSB5-provided 32-bit/33-MHz PCI bus.
•
The CSB5 provides a 32-bit/33-MHz PCI bus.
• The CIOB-X2 provides a 64-bit/100-MHz PCI-X bus and the 64-bit/133-MHz PCI-X bus.
This independent bus structure allows all three PCI buses to operate concurrently and provides
1.2 GB per second of I/O bandwidth.
2.2.5 CMIC-LE
The Champion Memory and I/O Controller (CMIC-LE) is the fourth generation product in
ServerWorks* Champion ServerSet Technology.
The CMIC-LE is built on top of the proven
components of previous generations like the Intel® Pentium® Pro Bus interface unit, the IMB
interface unit, and the DDR SDRAM memory interface unit.
The CMIC-LE integrates two main functional units: 1) an integrated high performance main
memory subsystem, and 2) an IMB bus interface that provides a high-performance data flow
path between the processor bus and the I/O subsystem. In addition to the above-mentioned
units, the CMIC-LE incorporates a Thin-Intra Module Bus (Thin-IMB) Interface.
Other features provided by the CMIC-LE include the following:
• Full support of processor bus protocol with multiprocessor support.
•
Full support of ECC on the memory interface.
• An in-order queue (twelve deep).
•
Full support of registered DDR ECC SDRAM DIMMs.
• Addressing support for 12 GB of 2-way interleaved SDRAM with 6 DIMMs sockets.
•
Memory scrubbing.
• Multiple-bit error detection and Multiple-bit error correction for 1-4 bits on one DRAM
within the same DIMM module (Chipkill*).