SMC Networks SMC91C95 - Manual (Page 124)

124
FIGURE 32 - 8-BIT MODE REGISTER CYCLES
FIGURE 33 - EXTERNAL ROM READ ACCESS
A0-15
(ISA)
AEN
nIORD
D0-7
nIOWR
t3
t3
t5
Z
VALID DATA OUT
Z
VALID DATA IN
t7
t8
VALID ADDRESS
t3
t5
t7
t8 Address, nSBHE, AEN Setup to Control Active
nIORD Low to Valid Data
Data Setup to nIOWR Rising
Data Hold after nIOWR Rising
Parameter min typ max units
25
30
9
40
ns
ns
ns
ns
VALID ADDRESS
t3
t4
t16
t17
Address Setup to Control Active
Address Hold after Control Inactive
nMEMRD Low to nROM Low
nMEMRD High to nROM High
25
20
0
0 25
30
ns
ns
ns
ns
A0-19
nMEMRD
ADDRESS VALID
D0-15
t3 t4
Z
Parameter min typ max units
BALE tied high