SMC Networks SMC91C95 - Manual (Page 108)

108
TIMING DIAGRAMS
FIGURE 18 - PCMCIA MEMORY READ TIMING
A[5:0], nREG
nCE1
nOE
D[15:0] DATA VALID
t1
t2
t3
t4
t5
t6
0 min
30 max
5 max
Parameter Min Typ Max Units
t1 Address Access Time 300 ns
t2 nREG Access Time 300 ns
t3 nCE1 Access Time 300 ns
t4 nOE Access Time 150 ns
t5 Output Disable Time from
nCE1 high 100 ns
t6 Output disable Time from nOE
high 100 ns
NOTE: Applies only when nWAIT is asserted by the SMC91C95.