Intel ARCHITECTURE IA-32 User Manual
Page 6
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Complex Instructions ...................................................................................................... 2-74
Use of the lea Instruction................................................................................................ 2-74
Use of the inc and dec Instructions ................................................................................ 2-75
Use of the shift and rotate Instructions ........................................................................... 2-75
Flag Register Accesses.................................................................................................. 2-75
Integer Divide ................................................................................................................. 2-76
Operand Sizes and Partial Register Accesses............................................................... 2-76
Prefixes and Instruction Decoding.................................................................................. 2-80
REP Prefix and Data Movement..................................................................................... 2-81
Address Calculations...................................................................................................... 2-86
Clearing Registers .......................................................................................................... 2-87
Compares ....................................................................................................................... 2-87
Floating Point/SIMD Operands....................................................................................... 2-88
Prolog Sequences .......................................................................................................... 2-90
Code Sequences that Operate on Memory Operands ................................................... 2-90
Latencies and Resource Constraints.............................................................................. 2-91
Spill Scheduling .............................................................................................................. 2-92
Scheduling Rules for the Pentium 4 Processor Decoder ............................................... 2-92
Scheduling Rules for the Pentium M Processor Decoder .............................................. 2-93
Vectorization ......................................................................................................................... 2-93
Miscellaneous ....................................................................................................................... 2-95
User/Source Coding Rules ............................................................................................. 2-97
Assembly/Compiler Coding Rules .................................................................................. 2-99
Tuning Suggestions...................................................................................................... 2-108
Checking for MMX Technology Support ........................................................................... 3-2
Checking for Streaming SIMD Extensions Support .......................................................... 3-3
Checking for Streaming SIMD Extensions 2 Support ....................................................... 3-5
Checking for Streaming SIMD Extensions 3 Support ....................................................... 3-6