Interphase Tech 4538 - Manual (Page 88)

PowerQUICC II Initializations
66 Interphase Corporation
• Refresh the SDRAM eight times (OP=001)
• Write the SDRAM Mode register (OP=011). For the main SDRAM placed on the
60x bus, the row/column address multiplexing is done externally, so the mode
register value must be coded in the column address of the dummy access following
the PSDMR programming.
• Reset the xDMR register OP field for normal operation (OP=000).
The refresh periods for the SDRAM devices are defined by one common Memory Refresh
Timer Prescaler Register (MPTPR) and by two individual SDRAM Refresh Timer
Registers (PSTR for the 60x bus and LSTR for the local bus).
On the 4538, no CPM local memory is present.
GPCM Controller Initialization
The initialization of a GPCM controller is done entirely in the bank Option Register (ORx).
On the 4538, the Flash EEPROM is controlled in bank 0 by a GPCM.
UPM Controller Programming
User Programmable Machine A (UPMA) is used to control accesses to the QuadFALC.
MPC603e Core Initialization
For full description of the MPC603e registers, read Motorola documents: MPC603e a
EC606e RISC Microprocessors User’s Manual (ref MPC603EUM/AD) and PowerPC
Microprocessor Family: The Programmer’s Reference Guide (ref MPRPPCPRG
– 01).
MMU Initialization
The 4538 local memory mapping is organized in such a way that the Block Address
Translation (BAT) mechanism can be used rather than the more complicated Segments and
Translation Look-aside Buffers (TLB) mechanism.
In the Boot Firmware, the MMU is initialized using the BAT mechanism. The cachable
areas are defined in the BAT blocks. Once the IBATx and DBATx special purpose registers
initialized, Address Translation is enabled for instruction and data in the Machine State
Register (MSR).
Cache Initialization
The data and instruction caches are automatically invalidated after a power-up or after a
hard reset, but not after a soft reset. The content of the instruction and data caches are easily
invalidated, using the Instruction Cache FLASH Invalidate (ICFI) and the Data Cache
FLASH Invalidate (DCFI) control bits in the HID0 register. Each bit must be set and
cleared in two consecutive moves to SPR (
mtspr ) operations to the HID0 register.