Interphase Tech 4538 - Manual (Page 8)

Contents
ii Interphase Corporation
PowerSpan I²O Registers
Interrupt Pins and Doorbell Usage
PCI to Local Interrupt (ATN)
Local to PCI Interrupt (–INTA)
Hardware and Software Resets Through the PowerSpan
Local Space Access From PCI Memory Space
Access to the FLASH EEPROM Through CompactPCI
PCI Memory Space and I/O Space Access From the PowerQUICC II
In-situ EPLDs Programming
Serial EEPROM Connected to the PowerSpan
Board Equipment Register
Vital Product Data (VPD)
Interphase-Specific Production Data and Boot Monitor Parameters
The FLASH EEPROM Boot Memory
The QuadFALC T1/E1/J1 Framer
The Ethernet Transceiver
TDM Bus Configurations
General
Multiplex Direct Mode
Independent Direct Mode
Switched Mode
Pass-Through Mode
CHAPTER 2 4538 Power-Up Initialization
Overview
PowerSpan Initialization
PowerSpan Hardware Configuration Word
PowerSpan Register Initialization Through the I²C Serial EEPROM
Other PowerSpan Initializations
PowerQUICC II Hardware Configuration Word
PowerQUICC II Initializations
PowerQUICC II System Interface Unit (SIU) Initialization
Internal Memory Map Register (IMMR)
Bus Configuration Register (BCR)
System Protection Control Register (SYPCR)
60x Bus Arbiter Registers (PPC_ACR, PPC_ALRH, and PPC_ALRL)
SIU Module Configuration Register (SIUMCR)
Bus Transfer Error Registers (TESCR1 and L_TESCR1)
Memory Controllers
SDRAM Controller and SDRAM Device Initialization
GPCM Controller Initialization
UPM Controller Programming
MPC603e Core Initialization
MMU Initialization
Cache Initialization
Communication Processor Module Initialization
I/O Port Initialization