Interphase Tech 4538 - Manual (Page 100)

T1/E1/J1 Framer Initialization
78 Interphase Corporation
SEC/FSC Configuration
The SEC/FSC signal of the QuadFALC is connected to CPM and is used for the TDM frame
synchronization clock (8 KHz synchronization pulse generated by one of the four DCO-
Rs). It must be configured as an FSC output by setting GPC1.CSFP1 to 1. Bit GPC1.CSFP0
allows selecting the active level (low or high). When using the pairing feature, FSC source
must match an active channel as for RCLK1: the source is selected with GPC1.FSS1 and
GPC1.FSS0 bits.
See Boot Firmware sources: TST\C\QFALC.C Function gvQFalcSetPortSyncSrc.
Independent Direct Mode
In independent direct mode, the four framers have their own rhythm. SWMODE_N = 1 and
COMCLK_N = 1.
System Interface
QuadFALC is connected to the CPM through four 2 MHz stream, corresponding to the four
T1/E1/J1 lines.
See Boot Firmware sources: tst\c\qfalc.c - Functions gvQFalcInitT1, gvQFalcInitJ1 and
gvQFalcInitE1.
The QuadFALC system multiplex mode must be disabled (GPC1.SMM = 0) with byte
interleaved format (SIC1.BIM=0), clocking rate at 2.048 MHz ( SIC1.SCC1/0=00) and
data rate at 2.048 MBit/s (SIC1.SSD1=0, FMR1.SSD0=0). Time-slot offset programming
was obtained by actual practice: XC0 = 0x00, XC1 = 0x03, RC0 = 0x00, RC1 = 0x03. The
receive buffer size must be set to two frames (SIC1.RBS1/0 = 00). The transmit buffer size
must be set to two frames (SIC1.XBS1/0 = 10). SIC3.RESX and SIC3.RESR must be set
to 0 (Synchronous Pulse Transmit (–SYPX) and Synchronous Pulse Receive
(–SYPR) are latched on first clock rising edge).
On the first channel, –SYPX (CMR2.IRSP = 0) and –SYPR (CMR2.IXSP = 0) inputs are
mapped to XPA1 and RPA1 pins respectively by setting the PC1 register to 0.
SCLKX_1 (used for the transmit system clock CMR2.IXSC = 0) and SCLKR_1 (used for
the receive system clock CMR2.IRSC = 0) must be configured as inputs by setting
PC5.CSXP and PC5.CSRP bits to 0.
On the other channel, the receive and transmit frame synchronous pulse are internally
generated (CMR2.IRSP = 1 and CMR2.IXSP = 1).
SCLKR_x is a 2.048 MHz dejittered receive system clock output (PC5.CSRP = 1)
generated by the DCO-R circuit (CMR2.IXSC = 1). The transmit system clock input
(PC5.CSXP = 0), SCLKX_x is sourced by the internal receive system clock (CMR2.IRSC
= 1).
RCLK1 Configuration as TDM Bus Clock
See Boot Firmware sources: tst\c\qfalc.c - Function gvQFalcSetPortSyncSrc.
RCLK1 signal of QuadFALC is recovered from the line and dejittered by DCO-R. It must
be configured as an active output (PC5.CRP = 1). RCLK2, RCLK3, and RCLK4 shall be
configured as inputs (PC5.CRP = 0).