Interphase Tech 4538 - Manual (Page 24)

The PowerQUICC II
2 Interphase Corporation
4538 Hardware Structure
Figure 1-1 shows the 4538 hardware structure:
Figure 1-1. 4538 Structure
The PowerQUICC II
The local CPU is a Motorola MPC8260 RISC embedded processor. The MPC8260
includes three major parts:
• An MPC603e core
• A System Interface Unit (SIU)
• A Communication Processor Module (CPM)
The MPC603e core is derived from the PowerPC™ 603e core and includes mainly the
integer core and the 16 KB data and 16 KB instruction caches.
The SIU includes a memory management unit and enables control of the external 60x local
bus (64-bit data width). The SIU also provides a local bus (32-bit data, 32-bit internal/18-
bit external address) used to enhance the operation of the Fast Communication Controllers
(FCCs). It can be used to store connection tables for ATM, buffer descriptors, or raw data
that is transmitted between channels. It is synchronized with the 60x bus and runs at the
same frequency. The 4538 does not provide CPM local memories.
The Communication Processor Module (CPM) is a super-set of the PowerQUICC II CPM
with additional capabilities. It features:
• Two Multichannel Communications Controllers (MCCs)
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