Motorola MVME197LE - Manual (Page 66)

Functional Description
4-8 User’s Manual
4
Refer to the VMEchip2, PCCchip2, and BusSwitch chapters in the MVME197LE,
MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference
Guide for detailed programming information.
Watchdog Timer
A watchdog timer function is provided in the VMEchip2. When the watchdog
timer is enabled, it must be reset by software within the programmed time or
it times out. The watchdog can be programmed to generate a SYSRESET*
signal, local reset signal, or board fail if it times out. Refer to the VMEchip2
chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board
Computers Programmer’s Reference Guide for detailed programming
information.
Software-Programmable Hardware Interrupts
Eight software-programmable hardware interrupts are provided by the
VMEchip2. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 chapter in the MVME197LE, MVME197DP, and
MVME197SP Single Board Computers Programmer’s Reference Guide for detailed
programming information.
Processor Bus Timeout
The BusSwitch provides a bus timeout circuit for the processor bus. When
enabled by the BTIMER register in the BusSwitch, the timer starts counting
when DBB* is asserted, and if the cycle is not terminated (TA*, TEA*, or
TRTRY* asserted) before the programmed timeout period, TEA* is asserted.
This timer is disabled if the access goes to the local peripheral bus.
Local Peripheral Bus Timeout
The MVME197LE provides a timeout function for the processor bus (MC88110
bus) and for the local peripheral bus (MC68040 compatible bus). When the
timer is enabled and a bus access times out, a Transfer Error Acknowledge
(TEA) signal is generated. The timeout value is selectable by software for 8
µ
sec, 64
µ
sec, 256
µ
sec, or infinite for the local peripheral bus. The local
peripheral bus timer does not operate during VMEbus bound cycles. VMEbus
bound cycles are timed by the VMEbus access timer and the VMEbus global
timer.
Interrupt Sources
MVME197LE MPU interrupts are channeled through the BusSwitch. They
may come from internal BusSwitch sources as well as from the PCCchip2 (IPL
inputs to the BusSwitch), the VMEchip2 (XIPL inputs to the BusSwitch), and