Motorola MC9S12GC-Family User Manual

Motorola Hardware

This manual is related to the following products:

MC9S12C-Family

Table of contents

Document Outline

Revision History
Table of Contents
List of Figures
List of Tables
Preface
- Table 0-1 List of MC9S12C and MC9S12GC Family members
- Table 0-2 MC9S12C-Family Package Option Summary
- Figure 0-1 Order Part number Coding
- Table 0-3 MC9S12C-Family Part Number Coding
- Table 0-4 MC9S12GC-Family Part Number Coding
- Table 0-5 Document References
  - Terminology
Section 1 Introduction
- 1.1 Overview
- 1.2 Features
- 1.3 Modes of Operation
- 1.4 Block Diagram
  - Figure 1-1 MC9S12C-Family Block Diagram
- 1.5 Device Memory Map
- 1.6 Detailed Register Map
- 1.7 Part ID Assignments
  - Table 1-3 Assigned Part ID Numbers
  - Table 1-4 Memory size registers
Section 2 Signal Description
- 2.1 Device Pinout
- 2.2 Signal Properties Summary
  - Table 2-1 Signal Properties
- 2.3 Detailed Signal Descriptions
- 2.4 Power Supply Pins
  - Table 2-2 MC9S12C-Family Power and Ground Connection Summary
Section 3 System Clock Description
- Figure 3-1 Clock Connections
Section 4 Modes of Operation
- 4.1 Overview
- 4.2 Chip Configuration Summary
  - Table 4-1 Mode Selection
  - Table 4-2 Clock Selection Based on PE7
- 4.3 Security
- 4.4 Low Power Modes
Section 5 Resets and Interrupts
- 5.1 Overview
- 5.2 Vectors
  - Table 5-1 Interrupt Vector Locations
- 5.3 Resets
  - Table 5-2 Reset Summary
Section 6 HCS12 Core Block Description
- 6.1 Device-specific information
  - Table 6-1 Device Specific Flash PAGE Mapping
Section 7 Voltage Regulator (VREG) Block Description
- 7.1 Device-specific information
Section 8 Recommended Printed Circuit Board Layout
- Table 8-1 Recommended External Component Values
- Figure 8-1 Recommended PCB Layout (48 LQFP)
- Figure 8-2 Recommended PCB Layout (52 LQFP)
- Figure 8-3 Recommended PCB Layout (80 QFP)
- Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator
- Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator
- Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator
Section 9 Clock Reset Generator (CRG) Block Description
- 9.1 Device-specific information
Section 10 Oscillator (OSC) Block Description
Section 11 Timer (TIM) Block Description
Section 12 Analog to Digital Converter (ATD) Block Description
- 12.1 Device-specific information
Section 13 Serial Communications Interface (SCI) Block Description
Section 14 Serial Peripheral Interface (SPI) Block Description
Section 15 Flash Block Description
Section 16 RAM Block Description
Section 17 Pulse Width Modulator (PWM) Block Description
Section 18 MSCAN Block Description
Section 19 Port Integration Module (PIM) Block Description
Appendix A Electrical Characteristics
- A.1 General
Appendix B Electrical Specifications
- B.1 Voltage Regulator Operating Conditions
  - Table B-1 Voltage Regulator Electrical Parameters
- B.2 Chip Power-up and LVI/LVR graphical explanation
  - Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
- B.3 Output Loads
  - Table B-2 Voltage Regulator - Capacitive Loads
- B.4 ATD Characteristics
- B.5 NVM, Flash and EEPROM
  - Table B-8 NVM Timing Characteristics
  - Table B-9 NVM Reliability Characteristics
- B.6 Reset, Oscillator and PLL
- B.7 MSCAN
  - Table B-13 MSCAN Wake-up Pulse Characteristics
- B.8 SPI
Appendix C Electrical Specifications
- Table C-1 Measurement Conditions
- C.1 Master Mode
- C.2 Slave Mode
- C.3 External Bus Timing
Appendix D Package Information
- D.1 General
- D.2 80-pin QFP package
  - Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
- D.3 52-pin LQFP package
  - Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)
- D.4 48-pin LQFP package
  - Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)
Appendix E Emulation Information
- E.1 General
  - Figure 19-1 Pin Assignments in 112-pin LQFP
- E.2 112-pin LQFP package
  - Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (ca...
Device User Guide End Sheet