B.4 atd characteristics, Table b-3 atd operating characteristics, Atd characteristics – Motorola MC9S12GC-Family User Manual
Page 99: B.4.1, Atd operating characteristics in 5v range, B.4.2, Atd operating characteristics in 3.3v range, Table b-3, Atd operating characteristics, B.4.1 atd operating characteristics in 5v range
Device User Guide — 9S12C128DGV1/D V01.05
99
B.4 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is
bonded to the VSSA pin.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the
ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
B.4.1 ATD Operating Characteristics In 5V Range
The Table B-3 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA
≤
VRL
≤
VIN
≤
VRH
≤
VDDA
.
This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
B.4.2 ATD Operating Characteristics In 3.3V Range
The Table B-3 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
SSA
≤
V
RL
≤
V
IN
≤
V
RH
≤
V
DDA
.
This constraint exists since the sample buffer amplifier can not drive
Table B-3 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= V
DDA
<=5V+10%
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
D
Reference Potential
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA/2
VDDA
V
V
2
C
Differential Reference Voltage
1
NOTES
:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
VRH-VRL
4.75
5.0
5.25
V
3
D
ATD Clock Frequency
f
ATDCLK
0.5
2.0
MHz
4
D
ATD 10-Bit Conversion Period
Clock Cycles
2
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
N
CONV10
T
CONV10
14
7
28
14
Cycles
µ
s
5
D
ATD 8-Bit Conversion Period
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV10
T
CONV10
12
6
26
13
Cycles
µ
s
5
D
Recovery Time (V
DDA
=5.0 Volts)
t
REC
20
µ
s
6
P
Reference Supply current
I
REF
0.375
mA