Sundance SMT166 - Manual (Page 24)

4.2.11 SATA3.0
Xilinx FPGAs such as the Virtex6 have got Rocket IOs that can be configured as
3Gbit/s SATA links (
URL:SATA HOST IP ). A license for a full core will be required in
order to implement a full SATA3.0 link.
4.2.12 RSLs to Master module
Two RSL lanes are available between each Virtex6 FPGA and one RSL connector on
the Master Module. RSL can sustain transfers at 200Mbytes/s per lane.
4.2.13 Inter-FPGA RSL links
Communication between FPGAs can be made via RSLs. Four are available between
FPGAs. Standard Sundance RSLs can achieve in excess of 300Mbytes/s per lane.
Virtex6 technology allows even faster rates so a transfer rate of 600Mbytes/s per
lane could be achieved.
Lanes are crossed-over on the PCB in order to have two identical firmware able to
exchange data via RSLs.
4.2.14 Inter-FPGA channels
A Channel is known as a parallel bus for transferring data. Being a parallel bus (as
opposed to serial) avoids un-deterministic latency due to FIFO and encoding,
generally used in serial transfer cores.
Sundance channels are not tied to a specific clock rate. Recently channels have been
successfully used at 250MHz, in DDR mode, meaning that transfer rate of up to
2Gbytes/s per channel can be achieved.
Two channels are implemented between the FPGAs.
Product Specification SMT166 Page 24 of 44 Last Edited: 17/06/2014 16:12:00