Samsung FLEX-MUXONENAND KFKAGH6Q4M Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for FLEX-MUXONENAND KFKAGH6Q4M Samsung
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 142 |
| Size: | 2.17 MB |
Show table of contents
Document Outline
- 4Gb Flex-MuxOneNAND M-die
- 1.0 INTRODUCTION
- 2.0 DEVICE DESCRIPTION
- 2.1 Detailed Product Description
- 2.2 Definitions
- 2.3 Pin Configuration
- 2.4 Pin Description
- 2.5 Block Diagram
- 2.6 Memory Array Organization
- 2.7 Memory Map
- 2.8 Registers
- 2.8.1 Register Address Map
- 2.8.2 Manufacturer ID Register F000h (R)
- 2.8.3 Device ID Register F001h (R)
- 2.8.4 Version ID Register F002h
- 2.8.5 Data Buffer Size Register F003h (R)
- 2.8.6 Boot Buffer Size Register F004h (R)
- 2.8.7 Amount of Buffers Register F005h (R)
- 2.8.8 Technology Register F006h (R)
- 2.8.9 Start Address1 Register F100h (R/W)
- 2.8.10 Start Address2 Register F101h (R/W)
- 2.8.11~15 Start Address3~7 Register F102h~F106h
- 2.8.16 Start Address8 Register F107h (R/W)
- 2.8.17 Start Buffer Register F200h (R/W)
- 2.8.18 Command Register F220h (R/W)
- 2.8.19 System Configuration 1 Register F221h (R, R/W)
- 2.8.20 System Configuration 2 Register F222h
- 2.8.21 Controller Status Register F240h (R)
- 2.8.22 Interrupt Status Register F241h (R/W)
- 2.8.23 Start Block Address Register F24Ch (R/W)
- 2.8.24 Start Block Address Register F24Dh (R/W)
- 2.8.25 NAND Flash Write Protection Status Register F24Eh (R)
- 2.8.26 ECC Status Register 1 FF00h (R)
- 2.8.27 ECC Status Register 2 FF01h (R)
- 2.8.28 ECC Status Register 3 FF02h (R)
- 2.8.29 ECC Status Register 4 FF03h (R)
- 3.0 DEVICE OPERATION
- 3.1 Command Based Operation
- 3.2 Device Bus Operation
- 3.3 Reset Mode Operation
- 3.4 Write Protection Operation
- 3.5 Data Protection During Power Down Operation
- 3.6 Load Operation
- 3.7 Read Operation
- 3.8 Synchronous Write(RM=1, WM=1)
- 3.9 Program Operation
- 3.10 Copy-Back Program Operation with Random Data Input
- 3.11 Erase Operation
- 3.12 Partition Information (PI) Block (SLC Only)
- 3.13 OTP Operation (SLC only)
- 3.14 DQ6 Toggle Bit
- 3.15 ECC Operation
- 3.16 Invalid Block Operation
- 4.0 DC CHARACTERISTICS
- 5.0 AC CHARACTERISTICS
- 5.1 AC Test Conditions
- 5.2 Device Capacitance
- 5.3 Valid Block Characteristics
- 5.4 AC Characteristics for Synchronous Burst Read
- 5.5 AC Characteristics for Asynchronous Read
- 5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset
- 5.7 AC Characteristics for Asynchronous Write
- 5.8 AC Characteristics for Burst Write Operation
- 5.9 AC Characteristics for Load/Program/Erase Performance
- 5.10 AC Characteristics for INT Auto Mode
- 6.0 TIMING DIAGRAMS
- 6.1 8-Word Linear Burst Read Mode with Wrap Around
- 6.2 Continuous Linear Burst Read Mode with Wrap Around
- 6.3 Asynchronous Read (VA Transition Before AVD Low)
- 6.4 Asynchronous Read (VA Transition After AVD Low)
- 6.5 Asynchronous Write
- 6.6 8-Word Linear Burst Write Mode
- 6.7 Burst Write Operation followed by Burst Read
- 6.8 Start Initial Burst Write Operation
- 6.9 Load Operation Timing
- 6.10 Superload Operation Timing
- 6.11 Program Operation Timing
- 6.12 Cache Program Operation Timing
- 6.13 Interleave Cache Program Operation Timing
- 6.14 Block Erase Operation Timing
- 6.15 Cold Reset Timing
- 6.16 Warm Reset Timing
- 6.17 Hot Reset Timing
- 6.18 NAND Flash Core Reset Timing
- 6.19 Data Protection Timing During Power Down
- 6.20 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low)
- 6.21 Toggle Bit Timing in Asynchronous Read (VA Transition After AVD Low)
- 6.22 INT auto mode
- 7.0 TECHNICAL AND APPLICATION NOTES
- 8.0 PACKAGE DIMENSIONS (TBD)