EVGA NFORCE 780I SLI - Manual (Page 106)

Post Codes
Award POST Codes
Co
de
Name Description
12 Test CMOS Test and Reset CMOS
13 Reserved
14 Load Chipset Load Chipset Defaults
15 Reserved
16 Init Clock Initialize onboard clock generator
17 Reserved
18 Init CPU CPU ID and initialize L1/L2 cache
19 Reserved
1A Reserved
1B Setup Interrupt
Vector Table
Initialize first 120 interrupt vectors with
SPURIOUS_INT_HDLR and initialize INT 00h-1Fh
according to INT_TBL
1C CMOS Battery
Check
Test CMOS and check Battery Fail
1D Early PM Early PM initialization
1E Reserved
1F Re-initial KB Load keyboard matrix
20 Reserved
21 HPM init Init Heuristic Power Management (HPM)
22 Reserved
23 Program chipset Early Programming of chipset registers
24 Init PNP Init PNP
25 Shadow VBIOS Shadow system/video BIOS
26 Clock Gen Init onboard clock generator and sensor
27 Setup BDA Setup BIOS DATA AREA (BDA)
28 Reserved
29 CPU Speed detect Chipset programming and CPU Speed detect
2A Reserved
2B Init video Initialize Video
2C Reserved