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Avago Technologies ACPL-P345-000E User Manual

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Once inspection is done, the evaluation board can be powered up in five simple steps. Figure 2 shows you how to test

the top or the bottom half-bridge inverter arms in simulation mode without the need for an actual power MOSFET.

Testing both arms of the half-bridge inverter driver (without a power MOSFET)

1. Solder a 10 nF capacitor across the gate and emitter terminals of Q1 or Q2. This is to simulate actual gate capacitance

of a power MOSFET.

2. Connect a +5 V DC supply (DC supply 1) across the +5V and GND terminals of CON1.
3. Connect another DC supply (DC Supply 2 with voltage range from 12 V ~ 20 V) across V

CC2

(pin 7 of IC2) and V

EE

(pin

5 of IC2) terminals of IC2a, respectively. This can be non-isolated for testing purposes.

4. Connect drive signals:

a. A 10 kHz 5 V DC pulse (at slightly < 50% duty) from a dual-output signal generator across IN1+ and IN1- pins of

CON1a to simulate microcontroller output to drive the lower arm of the half-bridge Inverter.

b. Another 10 kHz 5V DC pulse (at 180

° out of phase to the signal in 4a) from the dual-output signal generator across

IN2+ and IN2- pins of CON1b to simulate microcontroller output to drive the upper arm of the half-bridge inverter.

5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:

a. LED signal at the IN1+ pin with reference to (w.r.t.) GND.
b. LED signal at the IN2+ pin w.r.t. GND.

Note: The V

CC2b

supply of voltage close to V

CC2a

should then be successfully generated through the built-in bootstrap

components D3b and R6.

c. V

Ga

representing the output voltage of ACPL-P346/W346 (IC1a) at the gate pin of Q1a (or Q2a) w.r.t. V

Ea

.

d. V

Gb

(through an isolated probe) representing the output voltage of ACPL-P346/W346 (IC1b) at the gate pin of Q1b

(or Q2b) w.r.t. V

EB

.

10nF

In1+

In1-

Signal Input

+5V

Gnd

DC Supply 1

12~20 V

+

-

10nF

V

CC2b

+

-

In2+

In2-

Signal Input

5a

5b

5c

5d

V

Ea

V

Eb

DC Supply 2

1

2

4a

3

1

4b

Figure 2. Simple Simulation Test Setup of Evaluation Board

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