Grass Valley 8920DMX - Manual (Page 27)

8920DMX Instruction Manual 27
Functional Description
Input Equalizing Amplifier
The equalizing amplifier senses the voltage through its differential inputs.
It DC isolates the inputs and helps reduce the effect of stray capacitance
which lowers the impedance of the termination as frequency increases. The
differential input also improves the performance of the 8920DMX in the
presence of common mode hum and noise.
Clock Regenerator
The reclock stage is used to set mode and display the data rate. The Phase
Lock Loop circuit (PLL) uses a voltage controlled oscillator (VCO) to lock
to the clock of the incoming data.
Serial to Parallel Converter and EDH/EDA Error Processor
The serial to Parallel converter converts serial data stream to the parallel
data using the regenerated clock. Deserialized data passes through the
EDH processor. The EDH processor checks for possible data or bit errors in
the incoming data.
27Mhz PLL
From the incoming 27 MHz clock, the PLL generates the internal 27 MHz
and an approximate 27 MHz free running clock used if no input signal is
present.
Field Programmable Gate Array (FPGA)
The FPGA contains two independent blocks:
• 6.144 Mhz clock generator
• CPU interface
Using the DDS (Direct Digital Synthesis) method, the clock generator
inside the FPGA, together with the D-to-A converter and fast comparator
generates a 6.144 Mhz AES3 carrier clock from the incoming 27 Mhz.
The CPU interface provides connection between the board hardware and
CPU. From the FPGA, the CPU reads out information about current board
status and writes back user commands to the hardware.