Sundance SMT374 - Manual (Page 9)

Version 2.2 Page 9 of 29 SMT374 User Manual
Boot Mode
The two DSPs are called DSP-A and DSP-B. DSP-A is connected to the on-board
flash ROM that contains the Sundance bootloader and the FPGA bitstream.
Following reset, DSP-A will automatically load the first 1KB from the flash ROM into
its internal memory at address 0 and then start executing from there; DSP-B remains
held in reset. DSP-A now explicitly loads the next 3KB from ROM, giving the effect of
an initial load of 4KB. All this code is the Sundance bootloader, and it is made up of
three parts: FPGA configuration, processor configuration, and the Comport boot
procedure. FPGA configuration uses data in the ROM to configure the FPGA.
Processor configuration sets the processor into a standard state, copies its comport
boot procedure into a 2KB dual-port RAM (DPRAM) implemented in the FPGA, and
releases DSP-B from reset. DSP-B is configured to boot from this DPRAM, and this
leaves both DSPs executing their own copies of the Comport boot procedure.
The DPRAM is managed by writing to one of the board control registers (BCR)
implemented in a CPLD. The BCR bit functions are described in the
SMT6001 help
file .
Board Control Registers (BCRs)
DSP-A will take approximately 800ms to configure the FPGA following reset,
assuming a 150MHz clock. The external devices implemented in the FPGA (such as
comports) must not be used during this configuration.
It is safest to wait for the configuration to complete. Note that comports will appear to
be "not ready" until the FPGA has been configured.
The FPGA programming algorithm is not described here. It can be found in the boot
code.
DPRAM
The DPRAM in the FPGA is only intended to be used during this boot process; more
general use is not recommended. The DPRAM is accessible from the following
locations:
• DSPA has access to the DPRAM from address 0xB0100000
• DSPB has access to the DPRAM from address 0x90000000
EMIF Control Registers
The DSP has a single external memory interface (EMIF) which is 32 bits wide.