Sundance SMT363XC2 - Manual (Page 9)

Version 2.2 Page 9 of 27 SMT363XC2 User Manual
Architecture Description
NET+50
The NET+50 is a cost-effective, high-performance 32-bit network attached
microprocessor developed especially for high-bandwidth applications in Intelligent
Networked Devices. Based on ARM's architecture, it integrates 10/100Base-T
Ethernet MAC with an MII interface, a distributed 10-channel linking DMA controller
and a memory controller supporting all of the popular memory devices in use today.
This device is connected directly to an Intel LXT971 PHY device, which provides an
IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface.
Also, directly connected to the NET+50 are 16Mbytes of SDRAM, an RS232 level
converter and a 128KB Dual Port RAM (DPRAM).
LEDs 4 and 4 are controlled via PORTA bits 0 and 1.
DSP
The Texas Instruments DSP can run at up to 225MHz. The DSP is doted of 16MB
(optional 64MB) of SDRAM.
The DSP is a TMS320C6713 type.
An on-board 37.5MHz crystal oscillator provides the clock used for the DSP which
then multiplies this by for input to the DSP. DSP internally multiplies this up to the
required frequency, using a PLL.
Boot Mode
The DSP is connected to the on-board flash ROM that contains the Sundance
bootloader and the FPGA bitstream.
Following reset, the DSP will automatically load the data from the flash ROM into its
internal program memory at address 0 and then start executing from there. All this
code is the Sundance bootloader, and it is made up of three parts: FPGA
configuration, processor configuration and the Comport boot procedure. FPGA
configuration uses data in the ROM to configure the FPGA. A processor configuration
sets the processor into a standard state, copies its comport boot procedure into a
dual-port RAM (DPRAM) implemented in the FPGA, and releases the NET+50 chip
from reset. The Net+50 chip is configured to boot from this DPRAM.
The bootloader is executed. It will continually check the six comports until data
appears on one of them. This will next load a program in boot format from this
comport. Note that the bootloader will not read data arriving on other comports.
Finally the control is passed to the loaded DSP application.
It is safest to wait for the configuration to complete. Note that comports will appear to
be "not ready" until the FPGA has been configured.
The FPGA programming algorithm is not described here. It can be found in the boot
code.