Sundance SMT363XC2 - Manual (Page 11)

Version 2.2 Page 11 of 27 SMT363XC2 User Manual
CE1 - IO Control
Several I/O connections are required to control the NET+50 reset signal, upper flash
address signals, and the control signals for FPGA programming. These are all
accessed via the CE1 memory space and defined settings for some data lines.
D31 D30 D29 D0 Function
0 0 0 X Flash write
0 0 1 N NET+50 reset control. Reset(active low)=N
0 1 0 N Flash address A20 control. A20=N
0 1 1 N Flash address A21 control. A21=N
1 0 0 N FPGA PROG pin control. PROG(active low)=N
1 0 1 X FPGA CCLK pin control. Generates pulse on CCLK
1 1 0 N DPRAM semaphore enable when N=1
SDRAM
Memory space CE0 is used to access 16MB (or optional 64MB) of SDRAM over the
EMIF.
The speed of the SDRAM is dependent on the processor variant. Using the C6713,
the SDRAM will operate at 100MHz.
Using the C6713, the SDRAM operates at a programmable rate up to the maximum
allowed on the EMIF.
The EMIF CE0 memory space control register should be programmed with the value
0x00000030.
FLASH
An 8MB Flash ROM is connected to the DSP in the EMIF CE1 memory space. The
ROM holds boot code for the DSP, configuration data for the FPGA, the boot code
for the Net+50 chip and optional user-defined code.
A software protection algorithm is in place to prevent programs accidentally altering
the ROM’s contents. Please
contact Sundance for further information about re-
programming this device.
The CE1 memory space control register should be programmed with the value
0xFFFFFF23.