Sundance SMT339 v.1.3 - Manual (Page 4)

Version 1.2 Page 4 of 27 SMT339 User Manual V1.3
9 Cables and Connectors ................................................................................................................ 25
9.1 JP5 Virtex JTAG Header...................................................................................................... 25
9.2 JP7 Connector...................................................................................................................... 25
10 Where’s that Jumper?................................................................................................................... 27
Table of Figures
Figure 1 : Block Diagram for SMT339..........................................................................7
Figure 2 : Flow from Video Memory to Encoder ........................................................19
Figure 3 : Video Memory organisation in YCbCr output mode...................................20
Figure 4 : RGB565 organisation of the video memory ...............................................21
Figure 5 : Jumper Finder Diagram .............................................................................27
Table of Tables
Table 1 : Table of Abbreviations ..................................................................................5
Table 2 : DSP Memory Map ........................................................................................8
Table 3 : Virtex 4 Internal Peripherals..........................................................................8
Table 4 : EMIF Configurations .....................................................................................9
Table 5 : Virtex 4 LED Register bit Definitions...........................................................13
Table 6 : Virtex 4, Video Encoder Register................................................................14
Table 7 : Virtex 4, Video Decoder Register................................................................14
Table 8 : Video Port 0 and Decoder connectivity.......................................................15
Table 9 : Video Port 0 and Decoder Clock connectivity .............................................15
Table 10 : Video Port 0 Decoder Data to Video Port Data Mapping ..........................15
Table of Abbreviations
BAR Base Address Region
DMA Direct Memory Access
EPLD Electrically Programmable Logic Device
PCI Peripheral Component Interconnect
SDB Sundance Digital Bus