Sundance SMT339 v.1.3 - Manual (Page 16)

Version 1.2 Page 16 of 27 SMT339 User Manual V1.3
2.6.1.5 High Speed Nt (ZBT) Memory
There is just over 8Mbytes of high speed, no turnaround, (Nt) SRAM is connected to
the FPGA allowing high speed data storage capability to FPGA cores that require
external memory. The memory is based on two separate
Samsung K7N321801M
devices which are each 2M by 18-bit devices, allowing independent access of each
device
Please contact us if you require further information on using this device.
2.6.1.6 SLB Interface
The Sundance LVDS Bus ( SLB ) is a dual-port parallel interconnection link that is
capable of supporting data transfers at up to 700 MHz. Each port can be assigned
with a 16-bit differential bus, a clock and an over range differential lines.
The SLB is a link for data and clocks but also for control signals; it is based on a
Samtec QSH/QTH-DP series (0.5mm pitch) connectors.
The use of the SLB means that other customer specific input or output methods can
be supported without the need for re-design of the hardware. Some examples of IO
interfaces are listed below.
Input
• Camera Link
• Firewire
• CMOS
Sensor
• Fiber Channel
• DVI
Output
• USB
• IDE
• Fiber
Channel
• LCD/Plasma Display drivers
• DVI