Sundance SMT339 v.1.3 - Manual (Page 22)

Version 1.2 Page 22 of 27 SMT339 User Manual V1.3
The size of the EDMA is 180 (64bit transfers) for the Y channel which represent 720
pixels (as data is transferred line by line). The Cb and Cr channels must be half of
this representing the chroma content of the YCrYCb data stream.
For detailed information on setting up the DSP’s EDMA please refer to the TI user
guide
(TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller
Reference Guide ).
3.2 Video Decoder Setup
The video decoder can be setup to output data in a number of different modes.
Connectivity from the decoder the VIrtex 4 is via 2 separate data busses. One 8-bit
bus carries the Y data and the other 8-bit bus carries the Chroma information. Five
control lines are also connected for the various synchronising signals.
See Table 8 to Table 10 for details of how the hardware is mapped from the video
decoder to Video port 0.
The decoder can be setup to encode the data as BT656 with embedded syncs. This
allows just 8bits and a pixel clock to be used to transfer the images to the DSP.
Video port 0 can also be initialised to accept and decoder this data to the DSP’s
external SDRAM. See the
(TMS320C64x DSP Video Port/ VCXO Interpolated
Control (VIC) Port Reference Guide ) for more information.
4 JTAG
There are two separate JTAG chains on the SMT339 module. One allows the DSP
chain to be accessed while the other allows the Virtex 4 to be configured.
4.1 DSP JTAG Chain
This is used by code composer studio to access the DSP. There is provision to
extend the number of processors in the chain by adding a DSP via a SLB mezzanine
card. If this is added then the SLB JTAG bypass jumper (JP3) should be removed.
4.2 Virtex 4 JTAG chain
This can be accessed via the JP5 connector using Xilinx tools. The pinout for the
connector is shown in Section 10.