Sundance SMT339 v.1.3 - Manual (Page 12)

Version 1.2 Page 12 of 27 SMT339 User Manual V1.3
2.6 Virtex 4 FPGA
The FPGA on the SMT339 is a Virtex 4 FX60 device
(XC4VFX6010FF1152). It is
connected to the DSP’s EMIF and therefore allows its internal peripherals to be
accessed at 100MHz clock rates and a bus width of 64bits. This allows high speed
transfers to be initiated at request. It should, however, be noted that sustained large
transfer will affect the DSP’s peak performance if the DSP’s algorithm is running in
external SDRAM memory. To avoid this, the application can be run in internal DSP
memory.
Some of the FPGA’s features are listed below.
• The Virtex-4 enhanced PowerPC™ 405 core delivers 680 DMIPS performance at
450 MHz and the new Auxiliary Processor Unit (APU) controller
• 400+ MHz clock rates
• 2.8Mbits of internal block RAM available.
• Up to 444 18X18 embedded multipliers
• Extensive library of DSP algorithms
2.6.1 Virtex 4 Peripherals
The Standard firmware supplied with a SMT339 contains interfaces for the
peripherals listed below.
• Mapping of 2 Video Ports and related control registers
• Mapping of 2 communication ports
• LED Register Mapping
• Video Encoder Control Register
• Video Decoder Control Register