Sundance SMT339 v.1.3 - Manual (Page 14)

Version 1.2 Page 14 of 27 SMT339 User Manual V1.3
2.6.1.3 Video Encoder Register
The Video Encoder Register (0xA00D 8000) in the Virtex 4 allows various firmware
parameters to be setup correctly. By default Video Port 1 is connected to the video
encoder.
D7 D6 D5 D4 D3 D2 D1 D0
X X X D_MUX X TRI_C TVD ENC_RST
Table 6 : Virtex 4, Video Encoder Register
ENC_RST
– Encoder Reset, when ‘1’ the Reset pin on the video decoder is active.
TRI_C – When ‘0’ the Video port Control Lines (HSync and VSync) are driven by the
Encoder. The Encoder is in Master Sync mode. When ‘1’ the Video Port Sync Pins
are Tri-Stated.
TVD – TV Detected. Read only bit that returns a 1 in a load is detected on the CVBS
video output.
D_MUX – When this bit is ‘0’ the Video Port D[9..2] is fed directly to the encoder pins
D[7..0]. When set to a logic ‘1’ the data stream from the video port is assumed to be
RGB656 and is de-multiplexed from the Lower 16 bits of the Video Port 1 before
driving the encoder pins.
2.6.1.4 Video Decoder Register
The Video Decoder Register (0xA00E 0000) in the Virtex 4 allows various firmware
parameters to be setup correctly. By default Video Port 0 is connected to the video
decoder.
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X CTRL_DIR CLK_DIR DEC_RST
Table 7 : Virtex 4, Video Decoder Register
DEC_RST
– Decoder Reset, when ‘1’ the Reset pin on the video decoder is active.