Sundance SMT326v2 - Manual (Page 9)

Release Page 9 of 24 SMT326 DSP PC/ISA System User Guide
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Interface Logic
A small FPGA is used to provide all interface functions from the PC-ISA bus. This device performs
the functions necessary for a 'C44 communication port interface. The FPGA is loaded at power on
from a small serial ROM. All features of the FPGA can be customised by re-configuring this.
Communication Port Interface
An eight bit interface to the 'C44 is provided for by this device. Four bytes must be
transferred for each 32 bit word that is to be transferred to or from the 'C44. The 'C44
communications ports only deal with 32 bit quantities, although the data is transferred as
bytes.
This interface is compatible with the SMT300 and SMT322 and can thus support existing
operating systems such as 3L (TISLINK=SMT300,io:300).
Three registers reside inside this interface for the control of data transfers.
Link Reset / NMI
This register is accessed at PC I/O address 0x30C.
Asserting bit 0 of this register will put the 'C44 into reset.
Asserting bit 1 of this register will assert the NMI signal to the 'C44.
Link Status
The interface status can be determined by reading this register. It is accessed at PC
I/O address 0x304.
If bit 7 returns a '1' then data can be written to the link data register for transmission
to the 'C44 communications port. If bit 7 returns a '0', then the link data register is
full.
If bit 6 returns a '1' then data can be read from the link data register (this data is the
most recently transmitted word from the 'C44 down its communications port). If bit 6
returns a '0' then no data is available.
Link Data
Data from the PC is written here for transferral to the 'C44. It is accessed at PC I/O
address 0x30A.
The least significant byte must be written first. When all four bytes have been
written, the interface logic will transfer the whole 32 bit word to the 'C44. Bit 7 of the
link status register need only be read once per 4 bytes. Transfers must be in
multiples of 4 bytes.
Data from the 'C44 is available here for reading by the PC. The least significant byte
is read first. Transfers must be in multiples of 4 bytes. When bit 6 of the link status
register returns a '1', four bytes may be read without reading the link status register
again.
Using this polled data transfer mechanism, a data rate of approx. 350k bytes/s can
be achieved. This is due mainly to the limitation of the PC-ISA bus.