Sundance SMT326v2 - Manual (Page 4)

Release Page 4 of 24 SMT326 DSP PC/ISA System User Guide
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Interrupts
The processor may be interrupted from the ADCs on IIOF0. The ‘C44 should be set up as
edge triggered, as this signal lasts only 4 CODEC master clocks (80ns).
'C44 interrupt IIOF1 is routed to the PC Interface Logic but is currently uncommitted.
Reset
Reset to the board is performed by the PC-ISA signal RSTDRV.
A software reset to the 'C44 and communications port interface can be performed by the PC
writing a '1' to bit 0 of the link reset register (PC I/O address 0x30C).
Communications Ports
The 'C44 has four bi-directional communications ports (CPn - where n is 1,2,4 or 5) able to
sustain data rates of up to 20Mbytes/s.
On this board, one of the ports, P4, is connected to the PC-ISA communications port
interface. The other three are taken to ribbon cable connectors on the reverse of the board.
They are labelled CP1, CP2 and CP3. CP1 is connected to P1, CP2 to P2 and CP3 to P5.
(CP1=P1=FMS0; CP2=P2=FMS1 and CP3=P5=FMS2).
Additionally, ports P1, P2 and P5 are routed to the TIM site provided for expansion. P1 is
connected to TIM port 4, P2 to TIM port 5 and P5 to TIM port 1.
It must be noted that if a TIM is mounted in the TIM site then care must be taken to
ensure that only one device is driving the communications ports.